Speaker
Description
Summary
The Absolute Luminosity Monitor consists of 8 Roman Pots, each of them
containing identical readout architecture. A single Roman Pot consists of a 5 x 5
matrix of small structures called PMF.
Each PMF hosts 64 channel Maroc front-end chip and associated with it AlfaR
local readout controller. The latter one provides storage resources, a data
management and a serial communication interface between local and global
systems.
At each LHC clock, 64 bit wide data are made available on the output of Maroc.
Such data word is stored in 64 bit wide internal pipeline storage of AlfaR along
40 MHz LHC clock. Before being written, each bit of the input data word is
ANDed with respective bit of a mask register to allow for disabling of faulty
input channels. Depth of the pipeline is parameterized to allow for tuning of
the trigger latency to up to 256 clock cycles.
Each word is kept in the pipeline until is rejected or accepted by the first level
trigger. Upon decision, data are dropped or moved to another storage buffer -
an output derandomizer. To allow for checking of data alignment across local
readout systems, subset of the local bunch crossing and event counters’ states
are added to the accepted event data. This way, each data word written to the
derandomizer is extended to 71 bits.
The depth of the derandomizer is fixed and equals to 256 slots – sufficiently
enough to accommodate expected number of back-to-back positive decisions of
the first level trigger.
Event from the derandomizer is requested by the readout supervising chip
AlfaM as soon as a positive trigger decision is received. The corresponding data
word from the derandomizer is then serialized and sent to AlfaM via a
dedicated copper link.
AlfaM – the global readout controlled - is located on the motherboard card,
having connection to the global system as well as to 23 AlfaR chips belonging
to the PMF of a single Roman Pot. Once requested, the data transfers from all
underlying AlfaR controllers take place in the same time along centrally
distributed 40 MHz clock. After a fixed time interval, all data words from AlfaR
chips are de-serialized internally in input registers of AlfaM. Then subsequently
they are multiplexed and moved to the output data link buffer to form a data
block of particular event. Such block is sent over the gigabit optical output link
as soon as the link is free. Length of the message is fixed and for each event it
is ~2 Kbits.
Only when all input registers have been multiplexed and moved the output
buffer, AlfaM can request a new event data from the AlfaR controllers. Thus, in
order to make sure that none of back-to-back positive decisions of the first
level trigger is lost, they are buffered in the trigger FIFO of AlfaM. The depth of
this buffer is set to 256 slots – to match the depth of the derandomizing buffers
in the AlfaR controllers.
Apart from supervising the data flow, AlfaM provides a base for communication
between underlying AlfaR chips and the global system. Such communication is
realized using a simple SPI interface ran from the global system through ELMB
controller. This way one can read or write internal registers of AlfaM, AlraR or
Maroc chips or control operability of this system.
