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TWEPP-07 Topical Workshop on Electronics for Particle Physics

→ Europe/Zurich
Prague

Prague

Czech Republic
Francois Vasey (CERN)
Description
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The workshop will cover all aspects of electronics for particle physics experiments, and accelerator instrumentation of general interest to users.

It is continuing and expanding the scope of the former workshop on electronics for LHC and future experiments (LECC), LHC experiments will remain a focus of the meeting but a strong emphasis on R&D for future experimentation will be maintained, such as SLHC, CLIC, ILC, neutrino facilities as well as other particle and astroparticle physics experiments.

The purposes of the workshop are :

- to present results and original concepts for electronic research and development relevant to experiments as well as accelerator and beam instrumentation at future facilities

- to review the status of electronics for the LHC experiments

- to identify and encourage common efforts for the development of electronics

- to promote information exchange and collaboration in the relevant engineering and physics communities.

For access to the Prague website, please follow the link http://www.particle.cz/conferences/twepp07/homepage.aspx
Support
  • Monday, 3 September
    • Plenary session P1
      • 1
        Introduction and Welcome
        Speakers: Jan Dobes (Nuclear Physics Institute, ASCR), Jan Macek (Czech Technical University), Jan Ridky (Institute of Physics, ASCR), Jiri Horejsi (Charles University Prague)
        Slides
      • 2
        Particle Physics in the Czech Republic
        Several Czech universities and research institutes pursue active research in the field of particle physics. An overview of this research with the stress on experimental and instrumentation aspect will be presented.
        Speaker: Vaclav VRBA (Institute of Physics, ASCR, Prague)
        Slides
      • 3
        Organization
        Speaker: Zdenek Dolezal (Charles University Prague)
        Slides
      • 4
        The LHC machine status, commissioning plans and interface with the experiments
        The status of the ongoing Large Hadron Collider (LHC) installation is described with particular attention to the Long Straight Sections around the experiments. A summary of the present beam commissioning schedule will be given with some details on the beam conditions during first collisions. The second part of this talk will address in detail the experiment protection system from beam failures (including interlocks) and the exchange of data and control signals between the accelerator and the experiments.
        Speaker: Dr Daniela Macina (CERN)
        Paper
        Slides
      • 16:00
        break
      • 5
        The Time Projection Chamber for the ALICE Experiment
        ALICE will search for evidence for quark-gluon plasma, the state of matter which is believed to have existed just after the Big Bang, in head-on collisions of lead-ions at the LHC. This requires a very precise tracking capability to record the paths of thousands of particles produced in the collisions. ALICE is therefore built around the largest Time Projection Chamber (TPC) in the world. The task of large acceptance tracking in a heavy ion experiment is similar to that encountered in the NA49 and STAR experiments at the SPS and RHIC respectively. However, the extreme multiplicities of ion collisions at the LHC set qualitatively and quantitatively new demands making new designs indispensable. The construction and assembly of the ALICE TPC were completed in 2006. Before being lowered to the underground experimental area, an extensive commissioning was carried out with cosmic rays and tracks produced by a UV laser system. In January 2007, the TPC was transferred into the ALICE underground area, where it will be put into service by summer 2007 to be ready for first collisions in spring 2008. This paper presents an overview of the main components, with special focus on the front-end and readout electronics, and some of the most crucial aspects addressed by the R&D activities that have preceded the design and construction of the ALICE TPC. The commissioning, including preliminary results from the analysis of data on noise, electron diffusion, drift velocity, and spatial resolution, will be also presented.
        Speaker: Luciano Musa (CERN)
        Slides
      • 6
        Distributed Power Architectures for Computing Systems
        Nowadays computing systems comprise a large number of different processing equipment (servers, routers, etc.) with a total power consumption up to some megawatts. In these applications system-level issues like system and component architectures, modeling, control, power management, overall efficiency are of major concern. Different distributed power architectures are firstly reviewed, together with the most important converter topologies employed. Then, a particular emphasis is dedicated to the discussion of the Voltage Regulator Modules (VRMs) and their specific aspects. Finally, the future trend and applications of integrated digital controllers in distributed architectures, both at power management level and at the IC controller level, are discussed.
        Speaker: Prof. Giorgio Spiazzi (University of Padova, Department of Information Engineering - DEI)
        Slides
    • 18:00
      welcome drink
    • 7
      Executive summary
      Paper
  • Tuesday, 4 September
    • Plenary session P2
      • 8
        Fault-tolerant and radiation-hardened SPARC processors
        The paper will describe the development and status of radiation- hardened SPARC processors. The SPARC architecture was adopted by the European Space Agency (ESA) in 1992, and has since then been the baseline for most Eropean space missions. SPARC-based processor such as ERC32 are used to control many satellites, including the International Space Station. Newer devices based on the LEON acrhitecture are being developed, and are available on both radiation-hardened ASIC and FPGA technologies. A summary of availble LEON devices and software development tools will be provided in the paper.
        Speaker: Mr Jiri Gaisler (Gaisler Research AB)
        Slides
      • 9
        Field-programmable technology: today's and tomorrow's
        The latest field-programmable technology, with enhanced processing, storage and interface capacity, enables the development of powerful and flexible systems that can be customised for specific applications and operating conditions. This presentation describes recent field-programmable systems and tools which have been developed to optimise design quality and designer productivity, and illustrates their use in various application domains such as real-time data analysis, facilities for high-speed networks, and Monte Carlo simulation. The issues addressed include: how to make the best of today's field-programmable technology, and what can we expect of tomorrow's field-programmable technology?
        Speaker: Prof. Wayne Luk (Computer Engineering, Imperial College)
        Slides
    • 10:30
      break
    • Parallel session A1 - Systems, Installation and Commissioning 1 (DAQ, DCS, Cal)
      • 10
        Infrastructures and installation of CMS DAQ
        At the time of this paper, all hardware elements of the CMS Data Acquisition System have been installed and commissioned both in the underground and surface areas. This paper describes in detail the infrastructures and the different steps that were necessary from the very beginning when the underground control room was only a building yard to a working system collecting data fragment from ~650 sources and sending them to surface for assembly and analysis.
        Speaker: Dr Attila RACZ (CERN)
        Paper
        Slides
      • 11
        Implementation and performance of the Detector Control System for the electromagnetic calorimeter of the CMS experiment
        In this presentation we describe the main design objectives, the detailed specifications and the final layout of the Detector Control System (DCS) for the electromagnetic calorimeter (ECAL) of the CMS experiment. Emphasis is put on the system implementation and specific hardware and software solutions in each of its sub-systems. The latest results from the tests of final prototypes of these subsystems during the 2006 ECAL test-beam programme, as well as the installation and commissioning of the whole DCS at the CMS experimental construction site are also discussed.
        Speakers: Jovan Puzovic (VINCA Institute of Nuclear Sciences and Faculty of Physics, Belgrade), Serguei Zelepoukine (ETH Zürich; IHEP Protvino, Moscow)
        Paper
        Slides
      • 12
        Performance Study of the CMS Ecal Electronics using electrons from 15 GeV to 250 GeV
        The experimental conditions and physics goals of LHC experiments set challenging specifications for detectors and their readout electronics. The CMS Electromagnetic Calorimeter (Ecal) is an example of a complex system in which every component needs to be understood in detail in order to ensure the quality of the physics results. In 2006 9 ECAL supermodules were exposed to an electron test beam in the energy range from 15 GeV and 250 GeV. Many aspects of the calorimeter response have been studied in detail. We will describe the results of these studies, with emphasis on the contribution of the electronics to linearity, resolution and noise of the system.
        Speaker: Dr Stefano Argiro (European Organization for Nuclear Research (CERN))
        Paper
        Slides
      • 13
        New DAQ and Digitizing systems of CMD-3 Detector.
        The CMD-3 Cryogenic Magnet Detector for VEPP-2000 Collider is under construction now. This paper describes hardware part of new DAQ system. The unique features of this system is low EMI, low power and high speed. This is serial-backplane LVDS – media based system. The DAQ system is easy scalable and low-cost due to output to commercially available Fast Ethernet. Special attention is devoted to how DAQ interact with Trigger and Digitizing subsystems. As example the “T2Q” Readout and Signal Processing Board for Drift Chamber of CMD-3 detector are presented. This Board includes 16 wire processing channels which performs double-end wire readout for charge division measurements and time measurement. Each wire processing channel supplied with a micro-trigger to operate in Common-Stop CMD-3 Trigger environment. The unique features of this Board are very high dynamic range to ensure good dEdx and high accuracy time measurement. Low size and low power consumptions are achieved utilizing commercially available components only. It is shown specially designed low EMI high-speed serial backplane DAQ has virtually no pick-ups and allows on-board preamplifier and on-board ground decoupling.
        Speaker: Mr Alexander Ruban (BINP- Bunker Institute of Nucleare Physics, Novosibirsk, Russia)
      • 14
        A MAPS-based readout for Tera-Pixel electromagnetic calorimeter at the ILC
        For the ILC physics program, the detectors will need an unprecedented jet energy resolution. For the electromagnetic calorimeter, the use of a highly granular silicon-tungsten calorimeter has been proposed. The status of a silicon readout option, which uses Monolithic Active Pixel Sensors (MAPS), will be presented. This novel design provides extremely fine granularity with integrated binary readout. This leads to a "Tera-Pixel" electromagnetic calorimeter system. A overview of the MAPS concept will be given along with the advantages of this design. We present first results of the prototype sensor together with simulation results showing the expected detector performance.
        Speaker: Dr Giulio Villani (STFC Rutherford Appleton Laboratory)
    • Parallel session B1 - Trigger 1 Atlas
      • 15
        The ATLAS Level1 Level2 Trigger Integration
        The ATLAS detector is designed to study the proton proton collision at the center of mass energy of 14 TeV with the bunch crossing rate of 40 MHz. In order to reduce this rate down to the level at which the events will be fully reconstructed, the multi-level trigger system is being deployed. The level 1 (LVL1) trigger reduces the rate down to 75 kHz via the custom-built electronics. The Region of Interest Builder (RoIB) delivers the Region of Interest (RoI) records to the level 2 (L2LV) trigger which runs the selection algorithms with the commodity processors and brings the rate further down to ~3 kHz. Finally the Event Filter (EF) reduces the rate down to ~200 Hz for permanent storage. The LVL1, LVL2 systems will be overviewed. The cosmic ray data taking in situ using partial detectors, the full trigger system and the DAQ system will be discussed. Results on system functionality, consistency in the full hardware and software chain based on the cosmic data will be presented. The trigger system performance will be shown with some critical quantities obtained by running preselected simulated events through the trigger and dataflow chains.
        Speaker: Jinlong Zhang (Argonne National Laboratory (ANL))
        Slides
      • 16
        The ATLAS Level-1 Central Trigger
        The ATLAS Level-1 Central Trigger consists of the Muon-to-Central-Trigger- Processor Interface (MUCTPI), the Central Trigger Processor (CTP), and the Timing, Trigger and Control (TTC) partitions of the sub-detectors. The MUCTPI connects the output of the muon trigger system to the CTP. At every bunch crossing it receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six pT thresholds. The CTP combines information from calorimeter and the MUCTPI and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). The MUCTPI and the CTP provide trigger summary information to the data acquisition system (DAQ) and the Level-2 trigger for every event selected at the Level-1. They further provide accumulated and, for the CTP, bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The TTC partitions send timing, trigger and control signals from the CTP to the sub-detectors and receive busy signals which can throttle the generation of L1As. The Local Trigger Processors (LTPs) normally receive the TTC signals from the CTP but can also generate them locally. The LTP interface (LTPIF) modules allow to connect several LTPs for combined local running. The MUCTPI, the CTP and most of the TTC partitions of the ATLAS sub-detectors have been installed in the ATLAS experiment and are being used for commissioning tests with the trigger processors on the input and several sub-detectors as well as DAQ and Level-2 trigger on the output. Results of operating the Central Trigger in the experiment using trigger information from trigger processors connected to sub-detectors observing cosmic rays will be shown.
        Speaker: Dr Ralf Spiwoks (CERN)
        Paper
        Slides
      • 17
        First Measurements with the ATLAS Level-1 Calorimeter Trigger Preprocessor System
        The level-1 calorimeter trigger is a hardware-based system with the goal of identifying high-pt objects within an overall latency of 2.5us. It is composed of a preprocessor system which digitises 7200 analogue input channels, determines the bunch-crossing of the interaction and provides a fine timing and energy calibration; and two subsequent digital processors. The Preprocessor plays a central role during integration of the system as it provides digitisation and readout of calorimeter signals and serves as a digital signal source for the subsequent processors. Results of data taken with cosmic muons are shown, and the experience gathered during the system integration is described.
        Speaker: Victor Andrei (Kirchhoff-Institut fuer Physik/ Universitaet Heidelberg")
        Paper
        Slides
      • 18
        Commissioning of the Jet/Energy-sum and Cluster Processors for the ATLAS Level-1 Calorimeter Trigger System
        The ATLAS first-level calorimeter trigger is a hardware-based system designed to identify high-pt jets, electron/photon and tau candidates, and to measure total and missing Et. The trigger consists of a preprocessor system which digitises 7200 analogue inputs, and two digital multi-crate processor systems which find jets, measure energy sums, and identify localised energy deposits (electron/photon and tau candidates). In order to provide a trigger quickly enough, the hardware is parallel and pipelined. Experience so far of the jet/energy-sum and cluster processor system production, commissioning, and integration into ATLAS will be described.
        Speaker: Richard STALEY (University of Birmingham)
        Paper
        Slides
      • 19
        The ATLAS Barrel Level-1 Muon Trigger Sector-Logic/Rx off-detector trigger and acquisition board
        The ATLAS experiment uses a system of three concentric Resistive Plate Chambers (RPC) detector layers for the level-1 muon trigger in the air-core barrel toroid region. The algorithm looks for hit coincidences within different detector layers inside the programmed geometrical road which defines the transverse momentum cut. The on-detector electronics that provides the trigger and detector readout functionalities collects input signals coming from the RPC front-end. Trigger and readout data from on-detector electronics are sent via optical fibres to the off-detector electronics. Six or seven optical fibres from one of the 64 trigger sectors go to one VME Sector-Logic/RX module, that latter elaborates the collected trigger and readout data, and sends readout and trigger data respectively to the Read-Out Driver modules and to the Central Level-1 Trigger. We present the functionality and the implementation of the VME Sector-Logic/RX module, and results from the first cosmic ray run data collected using this module.
        Speaker: Dr Federico Spila (INFN, Sezione di Roma I)
        Slides
    • 13:00
      lunch
    • Parallel session A2 - Optoelectronics
      • 21
        Optical absorption in commercial single mode optical fibers induced by gamma rays and complex radiation fields
        The optical absorption in 13 SM fibers from 6 manufacturers was studied as a function of dose, dose rate, light power, wavelength and temperature. Two pure Si-core fiber exhibits extreme low radiation induced absorption.
        Speaker: Dr Thijs Wijnands (CERN)
        Paper
        Slides
      • 22
        Quality Control of the CMS Tracker and ECAL Installed Optical Cabling
        The readout and control optical links, developed for the CMS Tracker and ECAL at CERN, are approaching the final phase of the integration process at LHC Point 5. The individual component parts have been successfully integrated and connected at the innermost distributed patch-panels. Currently, efforts are concentrated on the multi-ribbon optical cables installation and connection to ribbon cables at the dense, in-line optical patch-panel inside CMS and to the racks at the backend patch-panel in the service cavern. Within the quality assurance programme, the quality control activities can give an online feedback during cable installation and provide an acceptance of the installed fibres. The final optical link lengths can also be measured as a precise input to the Tracker synchronization procedures. The recent integration experience and the quality control test system based on an Optical Time-Domain Reflectometer are described.
        Speaker: Daniel Ricci (CERN)
        Paper
        Slides
      • 23
        Joint ATLAS-CMS working group on optoelectronics for SLHC: Status Report
        Speaker: Francois Vasey (CERN)
        Slides
    • Parallel session B2 - Trigger 2 CMS and Atlas
      • 24
        Installation and Commissioning the CMS Regional Calorimeter Trigger Hardware into the CMS Level-1 Trigger
        The electronics for the Regional Calorimeter Trigger (RCT) of the Compact Muon Solenoid Experiment (CMS) have been produced, tested. The RCT hardware consists of 18 double-sided crates containing custom boards, ASICs, and backplanes. The RCT receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the CMS Global Calorimeter Trigger (GCT) after processing. Integration tests with the TPG and GCT subsystems have been sucessful. Installation is complete and commissioning of the final system is underway. During installation, pattern tests were used to validate 1026 TPG links and 108 GCT cables. Additionally, the RCT was part of several successive Global Runs, where an increasingly larger fraction of the full chain of the final Level-1 trigger system was tested. These tests, their results, and the RCT installation will be described.
        Speaker: Pamela Renee Klabbers (University of Wisconsin - Madison)
        Paper
        Slides
      • 25
        First Results on the Performance of the CMS Global Calorimeter Trigger
        The CMS Global Calorimeter Trigger(GCT) is the device within the CMS Calorimeter Trigger system which is assigned the tasks of finding and sorting forward, central and tau-jets, sorting isolated and non-isolated electron candidates and reading out all the calorimeter trigger data. The GCT system also provides for a cross-point switch which facilitates the connection between the Calorimeter and Muon Trigger systems. The GCT system uses 1.125 Gb/s optical links to concentrate the calorimeter data in eight processing cards and accomplishes the algorithm tasks by utilizing V2-Pro Xilinx devices. After a rapid development phase the GCT system has been produced and a large fraction of it has been installed at the CMS electronics cavern (USC-55). There it has been under test since March 07. Testing focused on two aspects of the GCT performance. First GCT was tested for synchronization and data transmission integrity using test pattern data injected in various places in the trigger chain. These tests aimed to establish that the GCT hardware performed as designed. Entire Monte Carlo events will also be propagated in the system to tests the algorithm performance. Results on the performance and testing of the GCT system at USC-55 are presented.
        Speaker: Dr Costas Fountas (Imperial College)
        Paper
        Slides
      • 26
        Modular Trigger Processing, The GCT Muon and Quiet Bit System
        The CMS Global Calorimeter Trigger system's HCAL Muon and Quiet bit function is being implemented with a novel processing architecture. This architecture utilizes micro TCA, a modern modular communications standard based on high speed serial links, to implement a processing matrix. This matrix is configurable in both logical functionality and data flow, allowing far greater flexibility than current trigger processing systems. In addition, the modular nature of this architecture allows flexibility in scale unmatched by traditional approaches. The Muon and Quiet bit system consists of two major components, a custom micro TCA backplane and processing module based. These components are based on Xilinx Virtex5 and Mindspeed crosspoint switch devices, bringing together state of the art FPGA based processing and Telcom switching technologies.
        Speaker: Mr Matthew Stettler (CERN)
        Paper
        Slides
    • 15:55
      break
    • Parallel session A3 - Joint ATLAS-CMS working group on optoelectronics for SLHC
    • Parallel session B3 - Trigger 3
      • 31
        The ALICE trigger electronics
        The ALICE trigger system (TRG) consists of a Central Trigger Processor (CTP) and up to 24 Local Trigger Units (LTU) for each subdetector. CTP receives and processes trigger signals from trigger detectors and output from CTP are 3 levels of hardware triggers L0, L1 and L2. 24 trigger detectors are dynamically partitioned into up to 6 independent clusters. The trigger information is propagated through the LTUs to the Front-end electronics (FEE) of each subdetector via LVDS cable and optical fiber. The trigger information, which is sent from LTU to FEE can be monitored online for possible errors by the newly developed TTCit board. After commissioning of TRG with each detector on surface, the ALICE trigger electronics has been installed and tested in the experimental cavern with appropriate ALICE experimental software. One setup is used for testing on the surface; the others are installed in experimental cavern. This paper describes the current status of ALICE trigger electronics, online error trigger monitoring and appropriate software for this electronics.
        Speaker: Marian Krivda (University of Birmingham, UK)
        Paper
        Slides
      • 32
        Data transmission and selection for the L0 calorimeter trigger of LHCb.
        This report describes the Selection Crate, designed by INFN for the L0 calorimeter trigger of the LHCb experiment. The Selection Crate is a modular system which consists in 8 Selection Boards (SB) used to select the most energetic clusters detected by the electromagnetic and hadron calorimeters, as well to evaluate other global trigger variables. A SB is equipped with 28 x 1.6 Gbps optical inputs and 3 x 1.6 Gbps optical outputs. The slow control is achieved by using a onboard diskless ethernet-booting CreditCard PC with a related GlueCard bus converter, while a TTCrq board provides the fast control TFC signals of the LHC TTC system. Each SB receives data from the front-end through 3 MPO ribbon connectors and sends data to the trigger decision unit through single channel optical links. All the optical links are suited for multimode, 1.6 Gbps, 850 nm fiber with sync patterns and 8B/10B coding. The optical transmitters used throughout the calorimeter have been designed by INFN Bologna. The optical transmitter boards are capable of sending on a single fiber up to 8 x 32bit at the LHCb clock of 40.08 MHz.
        Speaker: Mr Giulio Avoni (Istituto Nazionale di Fisica Nucleare (INFN))
        Paper
        Slides
      • 33
        A first-level track trigger architecture for Super-CMS
        We present a first architectural study of a first-level hardware track trigger for CMS at SLHC. The design of a hardware track trigger at 10^35cm-2s-1 is challenging. A primary constraint on implementation will be power consumption within the detector, in turn driven by the data transmission bandwidth to off-detector electronics. We therefore emphasise the minimisation of the data flow through local filtering of track candidates on the detector. The architecture presented does not comprise a stand-alone track trigger, but uses identified muon and calorimeter trigger objects to seed track-matching within an integrated first-level system.
        Speaker: Dr Dave Newbold (University of Bristol / Rutherford Laboratory)
        Paper
        Slides
  • Wednesday, 5 September
    • Plenary session P3
      • 34
        Electronics and Sensor Study with the OKI SOI process
        We are evaluating SOI (Silicon-On-Insulator) technology for radiation-hard electronics and monolithic radiation sensor applications. The process we used is a 0.15um CMOS, fully-depleted SOI technology developed by OKI Electronics Industry Co. Ltd. This SOI device has two Si layers; one is a thick substrate (handle wafer) which is Czochralski high-resistivity silicon, and another is SOI layer which is 40nm thick, low-resistivity silicon. Those Si layers are separated by a 200nm thick buried oxide (BOX) layer. The SOI layer is used to implement standard CMOS circuits. Although the handle wafer is normally just a physical structure in the SOI device, we developed a process to create p-n junctions in the handle wafer and connect them to transistors in SOI layer. Thus the handle wafer can be used as a radiation sensor. Since there is no mechanical bonding between the sensor and electronics, the capacitance of the sensor node is very low and it has excellent sensitivity to irradiation. By thinning the handle wafer, we can make low-material pixel detectors. We submitted first test designs at the end of 2005, and had successful results of test chips consisting of a 32x32 pixel detector, strip detectors and front-end electronics chips. At the end of 2006, we then performed our own MPW (Multi Project Wafer) run by collecting 17 different designs from US and Japanese universities/laboratories. The OKI SOI process and the results from this MPW run are presented.
        Speaker: Yasuo Arai (High Energy Accelerator Research Organization (KEK))
        Paper
        Slides
      • 35
        3D System Integration for high density interconnects
        3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity by combining devices of different technologies. Ultra thin silicon is the base of this integration technology. The fundamental processing steps will be described, as well as appropriate handling concepts. Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility, called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID), is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential to build multi-layer high-performance chip stacks and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues, a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.
        Speaker: Mr Robert Wieland
        Paper
        Slides
    • 10:30
      break
    • Parallel session A4 - Systems, Installation and Commissioning 2 (TK and Pix)
      • 36
        Electronics and Trigger developments for the Diffractive Physics Proposal at 220m from LHC-ATLAS
        The instrumentation consists of two sets of Roman Pots installed respectively at 216 and 224m on both sides from the ATLAS IP to measure with precision the position (<10 micrometers) and the timing (< 5 picoseconds) of the two back to back diffracted protons tracks. Each Roman Pot is equipped with several plans of edgeless silicon strip detectors read-out by a new version of the ATLAS SCT ABC chip with a longer latency (6.4 microseconds) and fast OR outputs defining a track segment. These inputs are to be combined in time with the ATLASLVL1 trigger ACCEPT signal. In addition these tracks are time filtered with a very fast timing detector (MCP-PMT) allowing to constraint further at LVL2 the position of the IP within one millimeter precision. The description of the electronics and trigger system as well as the various technical issues associated with such challenging experiment (clocks, cabling, cooling, time monitoring) will be presented. Preliminary test results of the position and timing devices will be given.
        Speaker: Mr Jean-François GENAT (LPNHE Paris6)
        Paper
        Slides
      • 37
        Production and Testing of the LHCb Outer Tracker Front End Readout Electronics
        The LHCb Outer Tracker is a straw drift detector with a modular design and a total of 55 000 readout channels distributed over a sensitive area of 12 double layers of 6x5 m^2 each. The main electronics readout requirement is the precise (~0.5 ns) drift time measurement at an occupancy of ~4% and 1 MHz readout. A total of 128 channels are read out by one Front-End box. About 450 FE-Boxes have been built. Quality Assurance during the production has been performed on single FE-Box components. The assembled FE-Box is finally commissioned using a special FE-Tester. The FE-Tester is a programmable pulser with a time resolution of 150 ps capable to simulate all the functionality of the readout mimicking the real detector. Consequently, problems have been found and solved resulting in good overall performance.
        Speaker: Eduard Simioni (NIKHEF, Amsterdam, The Netherlands)
        Paper
        Slides
      • 38
        The ALICE Silicon Pixel Detector system
        The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 half staves each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8,192 active cells, so that the total number of pixel cells in the SPD is ≈ 10^7. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The constraints on material budget detector module dimensions are very demanding. An overview of the electronics integration, test results and test procedures are presented.
        Speaker: Dr Alex Kluge (CERN)
        Paper
        Slides
      • 39
        Test and commissioning of the CARLOS control boards for the ALICE Silicon Drift Detectors
        The paper presents the test strategy and its results during the installation of the CARLOS end ladder board. This board is able to compress data coming from one Silicon Drift Detector (SDD) front-end electronics and to send them towards the data concentrator card CARLOSrx in counting room via a 800 MBit/s optical link. The paper describes the integration of the CARLOS end ladder boards, including its cooling system, mechanical supports, the low voltage distribution, various signal cables and optical fiber patch panels. The complexity and installation sequence require tests at each step of the installation.
        Speaker: Dr Filippo Costa (Department of Physics, University of Bologna, and I.N.F.N Bologna)
        Paper
        Slides
      • 40
        Towards the final ATLAS Pixel Detector Control System
        The innermost part of the ATLAS experiment is a pixel detector, built by around 1750 individual detector modules. To operate the modules, readout electronics and other detector components, a complex power supply and detector control system (DCS) is necessary. This includes a large number of crates, which house the different hardware components as well as a PC net, where the different control projects are running. To test the final detector after its assembly before it is installed in the ATLAS cavern a large test system was setup at CERN, which allows to operate ca. 10 % of the detector in parallel. Since autumn 2006 this system is in permanent operation. As nearly everywhere the final control hardware is used, its reliability and the performance of the control software could be investigated. An overview on our DCS hard- and software is given and we report on the experience with the control system. Susanne Kersten 'on behalf of Atlas Pixel Detector Collaboration'
        Speaker: Tobias Flick
        Slides
    • Parallel session B4 - ASICs 1 FE chips
      • 41
        Development of a small-scale prototype of the GOSSIP chip in the 0.13um CMOS technology.
        Abstract. The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a candidate to be a good alternative for silicon based pixel detectors. The Gossip chip is being developed to serve as a read-out array for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron enables 3D reconstruction of the particle’s track. For this purpose Time-to-Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13μm CMOS technology. The prototype includes a 16 by 16 pixel array. Each pixel is equipped with the front-end circuit, threshold DAC, and a high resolution 4-bit TDC. The chip will be available for testing in May 2007 and after initial tests it will be processed to build a prototype detector.
        Speaker: Mr Ruud Kluit (NIKHEF)
        Paper
        Slides
      • 42
        Steering and Readout Chips for DEPFET Sensor Matrices
        The ASICs required to operate DEPFET matrices - a fast analog switch and a drain current readout chip - are presented.
        Speaker: Mr Christian Kreidl (Universität Mannheim)
        Paper
        Slides
      • 43
        Development of a selftriggered high counting rate ASIC for readout of 2D gas microstrip neutron detectors.
        In the frame of the DETNI project a 32-channel ASIC suitable for readout of a novel 2D thermal neutron detector based on a hybrid low-pressure Micro-Strip Gas Chamber and solid 157Gd converter has been developed. Each channel delivers position information, a fast time stamp of 2 ns resolution and signal amplitude proportional to the energy. The time stamp is used for correlating the signals from X and Y strips while the amplitude is used for finding center of gravity of a cluster of strips. The timing and energy information are stored in derandomizing buffers and readout via token ring architecture.
        Speaker: Tomasz Fiutowski (AGH University of Science and Technology, 30-059 Krakow, Poland)
        Paper
        Slides
      • 44
        Test results on the n-XYTER ASIC, a self triggered, sparcifying readout ASIC
        n-XYTER is a 128 channel asynchronous, self triggered, self sparcifying readout ASIC developed as a front-end for neutron scattering detector applications. Due to the novel architecture it has attracted a considerable interest from future heavy ion experiments around the FAIR project. In particular for CBM and PANDA, n-XYTER is currently seen on one hand as the basis and starting point for a dedicated ASIC development on its own. On the other hand it will serve as the prototype readout electronic front-end for broad detector prototyping efforts that have just started and will span from silicon strips to gas detectors. The first dies of the n-XYTER ASIC are currently under thorough and intensive tests, so that the test results on operation and performance will be presented. Further, an outlook for FAIR related applications will be given.
        Speaker: Dr Christian Schmidt (GSI Darmstadt)
        Slides
      • 45
        VFAT2 : A front-end system on chip providing fast trigger information, digitized data storage and formatting for the charge sensitive readout of multi-channel silicon and gas particle detectors.
        The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC is presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal calibration, intelligent “fast OR” trigger building outputs, digital data tagging and storage, data formatting and data packet transmission with error protection. VFAT2 is designed to work in the demanding radiation environments posed by modern H.E.P. experiments and in particular the TOTEM experiment of the LHC. Measured results are presented demonstrating full functionality and excellent analog performance despite intensive digital activity on the same piece of silicon.
        Speaker: Dr Paul Aspell (CERN)
        Paper
        Slides
    • 13:00
      lunch
    • Parallel session A5 - Systems, Installation and Commissioning 3 (TK and Pix, Lumi)
      • 46
        Status of the ATLAS Pixel Detector
        The ATLAS silicon pixel detector is nearing completion for operation at the Large Hadron Collider at CERN. The ATLAS pixel detector contains approximately 80 million channels and 1744 detector modules. Electronics and module fabrication and testing is complete, as well as system integration of major elements of the pixel detector. The overall status of the ATLAS pixel detector will be presented, emphasizing systems issues and lessons learned in fabricating this new type of detector for hadron collider experiments.
        Speaker: Jean-Francois Arguin (LBL (Berkeley))
        Paper
        Slides
      • 47
        SCT Commissioning
        The Barrel and EndCap SCT detectors are installed in the ATLAS cavern. This talk will focus on the installation and first tests of the SCT in-situ. The thermal, electrical and optical services will be reviewed and some of the problems that were encountered during installation will be discussed. The first tests of the SCT in-situ will be described using the calibration scans.. The performance of the SCT will be described, with particular emphasis on the fraction of working channels and the noise performance. The effects of different grounding options have been studied. The noise occupancy has been studied in calibration and “physics” runs and the effects of the operation of the TRT have been evaluated.
        Speaker: Maiike Limper (NIKHEF)
        Paper
        Slides
      • 48
        SCT and TRT Performance from Cosmic Ray Runs
        The Barrel and Endcap SCT detectors have been integrated into the barrel and Endcap TRT detectors. There have been cosmic ray runs for the Barrel and Endcaps in the surface building (SR1) and after installation in the ATLAS cavern. This talk will focus on the most recent results. The procedure for timing in the SCT and TRT for Cosmic runs will be described as well as the procedures to ensure that the readout of the two detectors remained synchronous. Several tests were performed to see if the operation of the SCT (TRT) induced any noise in the TRT (SCT). The cosmic ray data are used to evaluate the SCT module and TRT straw efficiencies for MIPs and to verify that the noise occupancies are as low as expected from the calibration scans and from similar measurements in a controlled environment. This provides a critical test of the large-scale system performance of the integrated barrel SCT/TRT and end-cap SCT/TRT detectors The cosmic ray data also provide key data for initial alignment studies with tracks, and the most recent results are summarised.
        Speaker: Dr Heidi Sandaker (CERN)
        Paper
        Slides
      • 49
        System Design of the ATLAS Absolute Luminosity Monitor
        The ATLAS absolute luminosity monitor is composed of 8 roman pots symmetrically located in the LHC tunnel. Each pot contains 23 multi anode photomultiplier tubes, and each one of those is fitted with a front-end assembly called PMF. A PMF provides the high voltage biasing of the tube, the front-end chip and the local readout controller in a very compact arrangement. The 23 PMFs contained in one roman pot are connected to a motherboard used as an interface to the back-end electronics. The system allows to configure the front- end electronics from the ATLAS detector control system and to transmit the luminosity data over optical link.
        Speaker: Georges Blanchot (CERN)
        Paper
        Slides
    • Parallel session B5 - ASICs 2 ILC
      • 50
        Development of an ASIC for reading out CCDs at the vertex detector of the International Linear Collider
        The Linear Collider Flavour Identification Collaboration is developing sensors and readout electronics suitable for the International Linear Collider vertex detector. In order to achieve high data rates the proposed detector utilises column parallel CCDs, each read out by a custom designed ASIC. The prototype chip (CPR2) has 250 channels of electronics, each with a preamplifier, 5-bit flash ADC, data sparsification logic for identification of significant data clusters, and local memory for storage of data awaiting readout. CPR2 also has hierarchical 2- level data multiplexing and intermediate data memory, enabling readout of the sparsified data via the 5-bit data output bus.
        Speaker: Mr Peter Murray (STFC)
        Paper
        Slides
      • 51
        MAROC: Multi Anode Readout Chip
        MAROC is the readout chip designed for the ATLAS luminometer made of Roman pots. This ASIC has been realised in SiGe 0.35µm technology and is an evolution of the OPERA_ROC ASIC developed and installed on the OPERA experiment to auto-trigger and readout 64 channels Hamamatsu multi anode PMTs. Its main features are a 100% trigger rate for signal greater than 1/3 photoelectron, a charge measurement up to 30 photoelectrons with a linearity of 2% or better and a crosstalk less than 1%. A 12-bit Wilkinson ADC has been embedded to digitalise charge measurement. In order to check the functionalities of MAROC, laboratory tests have been performed and have showed a good global behaviour of the chip, which allows using it for beam tests of a complete Roman Pot at CERN during autumn 2007.
        Speaker: Mr Pierre BARRILLON (Laboratoire de l'Accélérateur Linéaire)
        Paper
        Slides
      • 52
        HARDROC, HAdronic Rpc Detector ReadOut Chip
        HARDROC is a complete readout chip in SiGe 0.35µm of the RPCs or GEMs foreseen for a Digital HAdronic CALorimeter (DHCAL) at the ILC. The ASIC integrates 64 channels of • fast low impedance preamplifier with 6bits variable gain (tunable between 0 and 4) • variable shaper (50-150ns) and Track and Hold to provide a multiplexed analog charge output up to 10pC. • variable gain fast shaper (15ns) followed by two low offset discriminators to autotrigg down to10 fC. The thresholds are loaded by two internal 10 bit- DACs. • A 128 deep digital memory to store the 2*64 discriminator outputs and bunch crossing identification coded over 24 bits counter. The design and measured performance of the chip will be presented.
        Speaker: Mr Christophe de LA TAILLE (IN2P3/LAL ORSAY)
        Slides
      • 53
        A 130nm CMOS Evaluation Digitizer Chip for Silicon Strips Readout at the ILC.
        A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16 deep-analog sampler triggered on input analogue sums, and parallel analog to digital conversion. Tests results of the full chain are reported, demonstrating the behavior and performance of the full sampling process and analog to digital conversion. Each channel dissipates less than one milliwatt static power.
        Speaker: Dr Jean-Francois Genat (CNRS/IN2P3/LPNHE)
        Paper
        Slides
    • 15:55
      break
    • Parallel session A6 - Systems, Installation and Commissioning 4 (Lumi, MU)
      • 54
        Development and Commissioning of the CMS Luminosity Monitor
        We discuss the development and commissioning of a luminosity monitor. It is based on hardware that provides real-time histograms of data from the forward hadronic (HF) calorimeters in CMS. Measuring the total energy deposition and occupancy in these detectors allows us to calculate the relative instantaneous luminosity of the collider on a bunch by bunch basis also useful for machine diagnostics. Once calibrated with measurements from the LHC we will be able to make the first proton-proton inelastic cross-section measurement. The methods for achieving this will be discussed, as well as the readout hardware design and implementation details.
        Speaker: Dr John Jones (Princeton University)
        Paper
        Slides
      • 55
        Time calibration of the LHCb Muon System
        The LHCb Muon System consists of about 122,000 readout channels. It plays a basic role in the first trigger level. The trigger requires 95% efficiency in Muon tracks detection. It is then necessary to reach a system time alignment at the level of about 2 ns. This alignment must be monitored against possible fluctuations due to changes in the detector operating conditions. We describe the custom instrumentation implemented at system level for time calibration, the strategy adopted, the procedure to be followed both for system alignment and monitoring, the control program realized for this purpose. We also illustrate first results obtained during the detector commissioning in the LHCb pit.
        Speaker: Caterina Deplano (INFN Cagliari)
        Paper
        Slides
      • 56
        CMS DT Chambers Read-Out Electronics
        Being close to completion of CMS installation, the three levels of the final read-out system of the Drift Tube (DT) chambers is presented. Firstly, the Read Out Boards (ROB), responsible for time digitalization of the signals generated by a charged particle track. Secondly, the Read Out Server (ROS) boards receive data from 25 ROB channels through a 240 Mbps copper link and perform data merging for further transmission through a 800 Mbps optical link. Finally, the Detector Dependent Unit (DDU) merge data from 12 ROS to build an event fragment and send it to the global CMS DAQ through a S-LINK64 output at 320 MB/s. DDU also receives synchronization commands from the TTC system (Timing, Trigger and Control), perform errors detection on data and send a fast feedback to the TTS (Trigger Throttling System). Functionality of these electronics has been validated in laboratory and in several test-beams, including the Magnet Test and Cosmic Challenge exercise that demonstrated proper operation and integration within the final CMS framework.
        Speaker: Cristina Fernandez Bedoya (CIEMAT)
        Paper
        Slides
      • 57
        CSC Data Acquisition System for CMS
        Details of the Cathode Strip Chamber (CSC) Data Acquisition (DAQ) system for the CMS experiment at the LHC will be described. The CSC system is large, consisting of 218K cathode channels and 183K anode channels. This leads to a substantial data rate of ~1.5GByte/s at LHC design luminosity (1034cm-2s-1) and the CMS first level trigger (L1A) rate of 100KHz. The DAQ system consists of three parts. The first part is on-chamber Cathode Front End Boards (CFEB), which amplify, shape, store and digitize chamber cathode signals, and Anode Front End Boards (AFEB), which amplify, shape and discriminate chamber anode signals. The second part is the on-detector Data Acquisition Motherboards (DAQMB), which control the on-chamber electronics and the readout of the chamber. The third part is the off-detector DAQ interface boards, which perform real time error checking, electronics reset requests and data concentration. It passes the resulting data to a CSC local DAQ farm, as well as CMS main DAQ. All electronics in the system employ FPGAs allowing programmability. In addition, several high-speed serial interface technologies are employed.
        Speaker: Dr Jianhui Gu (The Ohio State University)
        Paper
        Slides
      • 58
        The 1st Result of Global Commissioning of the ATLAS Endcap Muon Trigger System in ATLAS Cavern
        We will report on the ATLAS commissioning run from the view point of the Thin Gap Chamber (TGC), which is the ATLAS end cap muon trigger detector. So far, a half of TGC chambers with on-detector electronics have been already installed to the ATLAS cavern. To integrate all sub-detectors before the physics run starting from early 2008, the global commissioning run together with other sub-detectors has been performed from June 2007. We have evaluated the performance of the complete trigger chain of the TGC electronics and provide the trigger signal using cosmic-ray to the sub-systems in the global run environment.
        Speaker: Dr Takuya Sugimoto (Nagoya University)
        Slides
    • Parallel session B6 - ASICs 3 future
      • 59
        Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components
        Most of the microelectronics components developed for the first generation in LHC experiments have been defined and designed with very precise experiment specific goals and are hardly adaptable to other applications. In an effort to cover the needs for generic programmable components often needed in the real world, an industry-compatible Programmable Logic Device (PLD) and an industry- compatible Field-Programmable Gate Array (FPGA) are now under development. This effort is targeted to small volume applications or to the cases where small programmable functions are required to fix a system application. The PLD is a fuse-based, 10-input, 8-I/O general architecture device compatible with a popular commercial part. The FPGA under development is instead a 32×32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. SEU-robust registers are employed for configuration registers as well as for user data flip- flops. Test results for both chips will be presented.
        Speakers: Dr Kostas Kloukinas (CERN), Mr Sandro Bonacini (INPG, CERN)
        Paper
        Slides
      • 60
        a low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixels Sensor
        For CMOS monolithic active pixels sensor readout, we developed a 4 bit very low power analog to digital converter using a double sampling pipelined architecture. The converter consists of a non-resetting sample and hold stage followed by a 2.5 bit sub-ADC and a 2 bit flash. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.3mW at 3.3V supply voltage. It includes a fast power down input. The size for the layout is 80µm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20µm wide.
        Speaker: Mr Mokrane DAHOUMANE (Laboratoire de physique subatomique et de cosmologie (LPSC))
        A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors
        A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors
        Slides
      • 61
        The GBT, a Proposed Architecture for Multi-Gbps Data Transmission in High Energy Physics
        The future upgrade of the LHC accelerator, the SLHC, will increase the beam luminosity by a factor of ten leading to a corresponding growth of the amounts of data to be treated by the data transmission and acquisition systems. The development of the GBT ASIC addresses this issue providing a means to increase the bandwidth available to transmit the data to and from the counting room. The GBT architecture will provide the support to transmit simultaneously the three types of data required to run an experiment in a hostile radiation environment over a multipurpose link. This paper will describe the GBT architecture and some aspects of its detailed implementation.
        Speaker: Paulo Moreira (CERN)
        Paper
        Slides
      • 62
        A circuit topology suitable for the readout of ultra thin pixel detectors at SLHC and elsewhere
        Hybrid pixel detectors provide unrivalled pattern recognition capabilities at LHC vertex detectors. Further reducing the material budget is of crucial importance among the many challenges which must be addressed by the vertex systems at SLHC. We propose a two stage front-end pixel readout architecture whereby the discrimination is performed on the sum of the total charge deposited in four neighbouring pixels prior to readout of the analog or binary hit information per pixel. In this way it may be possible to reduce the detector thickness from some 100um to 50um while maintaining a high separation of signal, threshold and noise.
        Speaker: Dr Michael Campbell (CERN)
        Paper
        Slides
    • MicroElectronics User Group
      slides
      • 63
        MUG
    • 19:00
      Scientific Committee Meeting
    • 20:00
      Scientific Committee Dinner
  • Thursday, 6 September
    • Topical 1: Detector Power Supply and Distribution 1
      • 64
        System aspects of the ILC-electronics and power pulsing
        The detector development for the ILC experiments is driven by the bunch structure of the accelerator, short trains with long empty intervals, and high granularity of the detector. This requires the electronics to be integrated into the active detector volume. This talk exemplifies the concept for the electronics aiming for mechanical compactness through the CALICE-calorimeter. ASIC's nearby the active cells store the signals while the train and multiplexed data are transfered to the DAQ during the intervals between trains on a few signal lines. The compactness also requires components to be integrated into thin PCB's. The compactness and complexity of a system is also defined by the infrastructure. Therefore the concept aims for low power consumption to avoid active cooling. This can be reached by power pulsing synchronous to the train structure.
        Speaker: Mr Peter Goettlicher (Deutsches Elektronen Synchrotron (DESY))
        Paper
        Slides
      • 65
        ATLAS SCT Power Supply System
        The ATLAS SCT (semiconductor tracker) comprises 2112 barrel modules mounted on four concentric barrels of length 1.8m and up to 1m diameter, and 1976 endcap modules supported by a series of 9 wheels at each end of the barrel. Each module is powered by its own independent, floating low and high voltage power supplies, referenced to ground at the detector shield. Correspondingly each module has its own, distinct cable chain all the way back to the service cavern. This presentation outlines the structure and specification of the SCT Power Supply System, including the high level control software and operational model.
        Speaker: Mr Peter Phillips
        Paper
        Slides
      • 66
        Radiation-Tolerant Custom Made Low Voltage Power Supply System for ATLAS/TileCal Detector
        The Tile Calorimeter front-end electronics of the ATLAS detector is powered by 256 custom-made low voltage power supplies (LVPS) called LVBOX. Each LVBOX contains eight 150W DC/DC single-output modules transforming 200VDC input into various independent low voltage outputs (+3.3V, +/-5V, +/-15V). A local control and communication board using ELMB permits to monitor behavioral parameters (temperatures, Iin, Iout, Vin, Vout, sense lines reading) and trim Vout of each DC/DC module (Brick) using CAN Bus communication. The power supply is water cooled, is capable to survive a total integrated radiation dose of 40krad, and can work in external magnetic field higher than 0.02 Tesla. The LVPS is now manufactured in 256 production units.The 200VDC input voltage for these LVBOXes are delivered from 22 bulk power supplies HPS1 located in USA15 control room. Sixty-four auxiliary control and power supply boards (AUX Board) in the same control room are required to give power for the LVBOX monitoring and control circuits. Four LVPS Interlock Boards are capable to switch off all LVPS and HPS1 supplies in case of water cooling system leak or general switch off of the Tile detector.
        Speakers: Dr Bohuslav Palan (Institute of Physics), Mr Ivan Hruska (Institute of Physics)
        Paper
        Slides
    • 10:35
      break
    • Topical 2: Detector Power Supply and Distribution 2
      • 67
        The CMS Low Voltage System
        The low voltage system for the on-detector electronics of the CMS Experiment comprises 12090 channels of low voltage power supplies, requiring 1182 KVA of power at the entrance to the CMS facility at CERN. The severe radiation environment inside the CMS experimental cavern combined with an ambient magnetic field reaching up to 1.3 kGauss at the detector periphery severely limit the available choices of low voltage supplies, effectively ruling out the use of commercial off-the-shelf DC power supplies. Typical current requirements at the CMS detector front end range from 1A-30A per channel at voltages ranging between 1.25V and 8V. This requires in turn that the final stage of the low voltage power supply be located within ~10m of the front-end electronics, that is, on the detector periphery. Power to the CMS front-end electronics is stabilized by a 2 MVA UPS located in a CMS surface building. This UPS isolates the CMS detector from disturbances on the local power grid and provides for 2 minutes of autonomy following a power failure. This talk will describe the architecture of the CMS Low Voltage system as well as the considerations that went into its design.
        Speaker: Dr Sergei Lusin (Fermilab)
        Slides
      • 68
        The implementation of the power supply system of the CMS silicon strip tracker
        The power supply system of the silicon strip tracker of the CMS experiment provides HV bias and LV power to the 15 thousand silicon modules comprising the detector, arranged into 1944 "power groups" and 256 "control rings". Around 1200 power supply modules, disposed on 29 racks, operate in a "hostile" radiation and magnetic field environment, 10 m away from the beam crossing region. They power the detector through ~50 m long custom-designed "Low Impedance" cables, adopting the sensing technique to compensate the voltage drop. Separate board models are deployed for detector power groups and control rings. The required 48V power is provided by AC-DC converters installed on the same racks. This paper reports the experience with the implementation of the system, which requires a careful study of the rack layout, grounding scheme, power budget, heat dissipation on racks. Comprehensive Quality Assurance and burn-in programs ensure the performance of the system, establishing the protocol, shared with the board's manufacturer, for acceptance tests and failure detection.
        Speaker: Dr Simone Paoletti (INFN sezione di Firenze)
        Paper
        Slides
      • 69
        Power distribution for SLHC trackers: challenges and solutions
        Current silicon detector systems power each detector module independently. For large-scale detectors like the LHC trackers, tens of thousands of cables are needed to power the front-end electronics. At the price of added material, the conventional independent powering is just manageable. For the SLHC trackers, with a five- to ten-fold increase in the number of electronic channels and increased total current, independent powering becomes prohibitive. Solving the power distribution problem is a major challenge, which must be met to make tracking at SLHC possible. I will give an overview of alternative power distribution concepts, summarise the current R&D activities and discuss power distribution requirements from a system perspective.
        Speaker: Marc Weber (Rutherford Appleton Laboratory)
        Slides
      • 70
        Serial Powering of Silicon Sensors
        Serial powering of silicon sensors will reduce the volume of power cables, the passive material and power losses in cables of future silicon trackers by large factors. These benefits are crucial for silicon tracking at the Super-LHC. Noise performance and grounding and shielding of densely packaged modules are key challenges for serial powering. We extended our studies with six ATLAS Semiconductor Tracker (SCT) modules to enable noise measurements in different geometrical configurations and for various sources of injected noise. We will present measurements obtained with a silicon strip supermodule. We will discuss the specifications of radiation-hard custom serial powering circuitry.
        Speaker: Dr Giulio Villani (Rutherford Appleton Laboratory)
        Slides
    • 13:05
      lunch
    • Topical 3: Detector Power Supply and Distribution 3
      • 71
        Low Voltage Power Supply Incorporating Ceramic Transformer
        A low voltage power supply provides the regulated output voltage of a few volts from the supply voltage around 48 V. The low voltage power supply incorporates a ceramic transformer which utilizes piezoelectric effect to convert voltage. The ceramic transformer isolates the secondary from the primary, thus providing the ground isolation between the supply and the output voltages. The ceramic transformer takes the place of the conventional magnetic transformer. The ceramic transformer is constructed from a ceramic bar and does not include any magnetic material. So the low voltage power supply can operate under a magnetic field. The output voltage is stabilized by feedback. A feedback loop includes an error amplifier, a voltage controlled oscillator and a driver circuit. The amplitude ratio of the transformer has dependence on the frequency, which is utilized to stabilize the output voltage. The low voltage power supply is investigated on the analogy of the high voltage power supply similarly incorporating the ceramic transformer. Stability of the power supplies is studied from the theoretical viewpoint of stability. It is shown that the compensation, which has been applied to the high voltage ceramic transformer, could work similarly for the low voltage power supply.
        Speaker: Dr Masatosi Imori (The university of Tokyo)
        Paper
        Slides
      • 72
        High Radiation Resistant DC-DC Converter Regulators for use in Magnetic fields for LHC High Luminosity Silicon Tracker
        We have found at least one commercial Buck regulator with integrated inductor fabricated with 0.25µm CMOS technology. This device was exposed to a Cobalt 60 source at BNL; there was negligible effect to 100 mega rad dosage (when the exposure was terminated). System implementation issues are being evaluated.
        Speaker: Dr Satish Dhawan (Yale University)
        Paper
        Slides
      • 73
        Inductor based switching DC-DC converter for low voltage power distribution in SLHC
        In view of a power distribution scheme compatible with the requirements of future trackers in SLHC, we are evaluating the feasibility of on-board inductor based DC-DC step-down conversion. Such converter should be integrated and capable of operating in radiation environments and magnetic field. We present results concerning the choice of the CMOS technology for the integrated circuit, the research of magnetic components properly working in presence of high magnetic field, calculations of the expected efficiency and EM noise emission.
        Speaker: Mr Stefano Michelis (CERN-PH/MIC)
        Paper
        Slides
      • 74
        Topical Discussion
    • 16:20
      break
    • Poster session
      • 75
        A complete set of firmware for the TileCal Read-Out Driver.
        TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The Read-Out Driver (ROD) is the main component of the TileCal back-end electronics. The ROD is a VME 64x 9u board with multiple programmable devices which requires a complete set of firmware. This paper describes the firmware and functionalities of all these programmable devices, especially the DSP Processing Units daughterboards where the data processing takes place. Finally, some results obtained during the TileCal commissioning phase are presented.
        Speaker: Mr Alberto Valero Biot (Instituto de Fisica Corpuscular (IFIC) UV-CSIC)
        Paper
      • 76
        A Trigger/Timing Logic Unit for ILC Test-beams
        ILC not a triggered experiment, but during detector development it may be useful to operate in a triggered mode. A Trigger/Tagging Logic Unit (TLU) is described which allows triggered operation, with option of smooth transition to triggerless, data-driven mode. The TLU is being developed as part of the EUDET programme to develop test-beam infrastructure for ILC detector development.
        Speaker: Dr David Cussans (H.H. Wills Physics Laboratory)
        Paper
        Poster
      • 77
        ALIBAVA : A PORTABLE READOUT SYSTEM FOR SILICON MICROSTRIP SENSORS
        A portable readout system for micro-strip silicon sensors has been developed. The system uses an analogue pipelined readout chip, which was developed for the LHC experiments. The system will be used to characterise the properties of both non-irradiated and irradiated micro-strip sensors. Heavily irradiated sensors will be operated at the Super LHC. The system hardware has two main parts: a daughter board and a mother board. The daughter board contains two readout chips, analogue data buffering, power supply regulation and chip-to-sensor fan-in structures.. The mother board is intended to process the analogue data that comes from the readout chips and from external trigger signals, to control the whole system and to communicate with a PC via USB. There is provision for an external trigger input (e.g. scintillator trigger) and a synchronised trigger output for pulsing an external excitation source (e.g. laser system). A prototype of the system will be presented as well as early measurements operating a silicon micro-strip sensor in a laser setup.
        Speaker: Mr Ricardo Marco (IFIC-Instituto de Física Corpuscular, Universidad de Valenca-CSIC, Valencia, Spain)
        Paper
      • 78
        Calibration and performance tests of the Very-Front-End electronics for the CMS electromagnetic calorimeter
        The Very-Front-End electronics processing signal from photodetectors of the CMS electromagnetic calorimeter, have been put through extensive test program to guarantee functionality and reliability. The final characteristics of the VFE boards designed for the calorimeter barrel and endcaps are resented. The results, which have been also verified during test beam at CERN, confirm the high quality of the boards production and show that the CMS detector specifications are reached.
        Speaker: Jan Blaha (Institut de Physique Nucleaire de Lyon (IPNL))
        Paper
        Poster
      • 79
        CARLOSrx: an on line Data Acquisition system for ALICE ITS SDD
        The data concentrator card CARLOSrx is a readout board developed for the ALICE ITS Silicon Drift Detector (SDD) experiment held at CERN. CARLOSrx is a 9Ux400 mm VME board, containing 4 FPGAs with the purpose of processing data coming from 12 SDD detectors and sending them to a computer running the DATE software. Twentyfour boards are installed for SDD. We have implemented and tested a new firmware version of CARLOSrx able to communicate with 12 SDD detectors, trigger system and DAQ software. The paper presents the results of these tests.
        Speaker: Dr Costa Filippo (Department of Physics, University of Bologna, and I.N.F.N Bologna)
        Paper
      • 80
        Design of an integrated particle detector-cell based on latchup effect
        The paper describes a novel approach to detect particles by means of an integrated device susceptible to latchup effects; it is proposed as a powerful means of achieving the precise detection and positioning of a broad range of particles with a micrometer spatial resolution. The cell is designed using state-of-the-art AMS 0.35 micron BiCOMS technology. We show the design of a mixed-mode Bipolar-MOS circuit that is going to be fabricated and tested. Previous investigations indicate that the recognizable charge might be comparable to that collected into to-date detectors. The idea is proposed for possible a implementation as beam monitor or ion-selector in future high-energy experiments.
        Paper
        Poster
      • 81
        Design of on-chip data sparsification for a mixed-mode MAPS device
        The device described in the paper is built up of a bidimensional matrix of MAPS, already designed and fabricated in the past by the SLIM5 Collaboration, and of an off-pixel digital readout sparsification. The readout logic is based on std-cells and implements an optimised token-like technique. It is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future HEP experiments. In particular, the readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.
        Speaker: Dr Alessandro Gabrielli (INFN & Physic Department of Bologna University Viale Berti Pichat 6/2 40127 Bologna Italy)
        Paper
        Poster
      • 82
        Development of a Front-End Electronics for Pico-second Resolution TOF Detectors
        We have proposed using 2" by 2" micro-channel plates (MCP-PMTs) with a novel equal-time anode and with capacitive return path coupling to measure the time-of-flight of relativistic particles, with the goal of being able to construct large-area TOF detectors with a resolution of 1 psec. The proposed front-end customer chip is a time stretcher with 1ps resolution, building with IBM 0.13um SiGe BiCMOS process. the preliminary designs and simulations for the front-end ASIC chip will be presented in this paper.
        Speaker: Fukun Tang (Enrico Fermi Institute - University of Chicago)
      • 83
        Digital part of SiPM Integrated Read Out Chip ASIC for ILC hadronic calorimeter
        SPIROC (SiPM Integrated Read Out Chip) is the Very Front End ASIC that reads ILC hadronic calorimeter SiPM. It integrates a very complex digital part which performs many functions and manages Acquisition, A/D Conversion and data Read-out. The Acquisition module manages Switched Capacitor Array in which charge and time are stored. This is done by an asynchronous module to meet time requirements. This part manages 36 channels with a depth of 16 for each. The conversion step permits to convert analogue data into digital data by driving an integrated Wilkinson ADC. Data are stored into an integrated 4K bytes memory. The read out step handles the communication between chips and sendout of data. ASIC are daisy chained to minimize lines between boards.
        Speaker: Mr FREDERIC DULUCQ (Laboratoire de l Accélérateur Linéaire)
        Paper
        Poster
      • 84
        Distribution of the Timing, Trigger and Control Signals in the Endcap Cathode Strip Chamber System at CMS
        This paper presents the implementation of the Timing, Trigger and Control (TTC) signal distribution tree in the Cathode Strip Chamber (CSC) sub-detector of the CMS Experiment at CERN. The key electronic component, the Clock and Control Board (CCB) is described in detail, as well as the transmission of TTC signals from the top of the CSC system down to the front-end boards.
        Speaker: Mr Mikhail Matveev (Rice University)
        Paper
      • 85
        ELMB Microcontroller Firmware and SCADA Integration for the LHCb Muon Detector Readout Control System
        The LHCb Muon Detector System will be equipped with about 1400 high efficiency chambers (Multi-Wire Proportional Chambers and Triple-GEM detectors) which will host a total of 7500 front-end boards, each receiving 16 readout channels and having 93 registers for access. A distributed PC network runs the supervision program and allows download of start-up settings and procedures, and upload of data logs. This document presents an outline of the LHCb Muon Detector Readout Control System and recent improvements regarding mainly the ELMB (Embedded Local Monitor Board) microcontroller firmware and the Supervisory Control And Data Acquisition (SCADA) system in use, PVSS.
        Speaker: Dr Rafael Nobrega (INFN Sez. Roma)
        Paper
      • 86
        Final Test at the Surface of the ATLAS Endcap Muon Trigger Chamber Electronics
        For the detector commissioning planned in 2007, a sector assembly of the ATLAS muon-endcap chamber and final test at the surface for the assembled electronics are progressed in CERN intensively. For the test, we built up the DAQ system using test pulse of two types and cosmic ray pulse. So far, 60% of all 320,000 channels have been already tested and most of them were installed into the ATLAS pit. In this presentation, we will describe the DAQ systems and mass-test procedure in detail, and report the result of electronics test with some actual experiences.
        Speaker: Takashi Kubota (ICEPP, University of the Tokyo)
        Paper
      • 87
        FPGA based Readout Logic of the Front-end Electronics of the Absolute Luminosity Monitor
        Readout of the front-end electronics of the Absolute Luminosity Monitor is controlled by programmable devices. AlfaR is a local readout controller which reads digitized data with LHC clock and keeps them until validation of the first level trigger. Once validated, data are moved via serial bus to further part of the readout chain supervised by AlfaM chip. This global readout controller manages 23 AlfaR devices and provides a platform for communication with a higher level system. For each accepted event, a block of data from all 23 AlraR controllers is sent from AlfaM over serial optical link. There are 8 such readout systems in whole Absolute Luminosity Monitor.
        Speaker: Wieslaw Iwanski (CERN, CH-1211 Geneva 23, Switzerland, INP PAN, Cracow, Poland)
        Paper
      • 88
        Installation and Commissioning of the CMS Timing, Trigger and Control Distribution System
        The Timing, Trigger and Control (TTC) distribution system must ensure high-quality clocking of the CMS experiment to allow the physics potential of the LHC machine to be fully exploited. This key system provides the synchronization tools – bunch clock, first level Triggers and fast commands – that enable all sub-detector systems to take data for the same LHC collision. The challenges of its installation are described, along with the tools used to commission the system and verify that its design goals are met.
        Speaker: Dr Jan Troska (CERN)
        Paper
        Poster
      • 89
        MAPS in 130 nm and 90 nm triple well CMOS technologies for HEP applications
        In this work deep N-well CMOS monolithic active pixel sensors (DNW-MAPS) are presented as an alternative approach to signal processing in high energy physics experiments. Based on different resolution constraints, some prototype MAPS, suitable for applications requiring different detector pitch, have been developed and fabricated in 90 nm and 130 nm triple well CMOS technologies. Experimental results from the characterization of the test structures with different features will be presented together with TCAD and Monte Carlo simulations intended to study the device substrate properties in terms of charge diffusion and charge sharing among pixels.
        Speaker: Mr Enrico Pozzati (Università di Pavia)
        Paper
        Poster
      • 90
        Optimization of amplifiers for MAPS
        High precision particle tracking and imaging applications require position sensitive detectors with high granularity, good radiation tolerance, low material budget, fast read-out and low power dissipation. Monolithic Active Pixel Sensors (MAPS) fabricated in a standard microelectronic technology provide an attractive solution for these demanding applications. The signal-to-noise ratio of MAPS can be increased by using in-pixel amplifiers. The compromise between speed, noise, gain and power consumption has to be achieved in the design of the amplifier. The charge collection efficiency and total capacitance at the amplifier input is influenced by the size of charge collecting diode. Therefore, in order to achieve better MAPS performances, both the geometry of the charge collecting diode and the amplifier design have to be considered in the optimization process. In this work different amplifier designs and geometries of the charge collecting diode are proposed. The characterization measurements of the amplifiers fabricated in AMS 0.35 um OPTO technology will be presented. The electronic properties of the amplifiers calculated with Spectre circuit simulator and the charge collection efficiency simulated with ISE-TCAD package will be compared with the measurements. The advantages and drawbacks of the implemented designs will be discussed.
        Speaker: Andrei Dorokhov (IPHC)
        Paper
      • 91
        Proposal of a readout technique for low-pitch pixel devices
        The up-to-date pixel detectors applied to HEP in LHC experiments implement 2D matrixes of sensitive elements that are basically readout via token-based techniques, according to external trigger signals. As the readout time is one of the drawbacks of large matrix devices, because it implies long detector dead times, here it is described a novel readout architecture of pixel devices, which exploits the features of deep-submicron CMOS technologies and should be considered for low-pitch pixel devices. This allows for future applications not only on general pixel detectors but also on trackers and trigger systems, wherever an on-chip data reduction/sparsification is considered.
        Speaker: Dr Alessandro Gabrielli (INFN Sezione di Bologna and Bologna University- Physics Department)
        Paper
        Poster
      • 92
        Proposal, development and test of an analog front-end electronic board for the Nemo telescope.
        Development, realization and test of an electronic data acquisition-board for the NEMO (NEutrino Mediterranean Observatory) collaboration are described in this work. The collaboration is involved in R&D for the construction of a deep underwater km^3 scale Cherenkov neutrino telescope in the Mediterranean sea. Thousands of optical modules are equipped with a photo multiplier tube and an electronic circuit for data acquisition and transmission. This work shows a possible solution for the front-end board compatible with an analog sampling chip; this data acquisition system has been developed to be fully compliant with the data transmission system of the Nemo Phase-1 apparatus.
        Speaker: Dr Filippo Maria Giorgi (INFN Bologna & Università degli studi di Bologna)
        Paper
        Poster
      • 93
        R/O Device based on USB1.0 for Spectroscopy DAQ
        A novel read-out (R/O) device based on universal series bus (USB1.0) for spectroscopy data acquisition (DAQ) together with software controlling analog-to-digital converters (type of Canberra, model 8715) will be presented. The interface exploiting the USB1.0 standard has two advantages: USB1.0 is spread out on all platforms and almost computers are equipped with this communication port; and, the speed of such devices (about 1Mb/s) is sufficient for spectroscopy with average number of events detected per second at the level up-to 50kHz. FTDI chips together with prepared software libraries of the Future Technology Devices International Ltd. were used for the realization of several examples of the read-out device. The response of the constructed devices was compared with the response of a Cicero multi-channel analyzer made by Silena. Equal devices were also tested using statistical tests with intention to verify their perfect functionality as well as their long-term stability. Results of these tests will be also presented.
        Speaker: Mr Petr Masek (FEE CVUT Prague, Czech Republic)
        Poster
      • 94
        Results and Consequences of Magnet Test and Cosmic Challenge for the CMS Barrel Muon Alignment System
        In the last year – as part of the CMS test called Magnet Test and Cosmic Challenge (MTCC) - about 25% of the full CMS Barrel Muon Alignment System was built and operated. The configuration enabled us to test all the elements of the system and its function under real conditions. In the paper the setup –including the read-out and control- is described and the first preliminary results are presented. The correct operation of the system has been demonstrated. About 500 full measurement cycles have been recorded and evaluated.
        Speaker: Dr Géza Székely (MTA Atomki, Hungary)
      • 95
        SKIROC : A FRONT-END CHIP TO READ OUT THE IMAGING SILICON-TUNGSTEN CALORIMETER FOR ILC
        This abstract describes the new front end ASIC designed for the silicon tungsten electromagnetic calorimeter called SKIROC. This new chip embeds the main features required for the ILC final detector.
        Speaker: Mr Julien Fleury (LAL - Orsay)
        Paper
      • 96
        Software environment for controlling and re-configuration of Xilinx Virtex FPGAs
        The Time Projection Chamber (TPC) is one of the sub-detectors of the ALICE detector that is currently being commissioned as a part of the Large Hadron Collider (LHC) at CERN. The Detector Control System (DCS) is used for control and monitoring of the system. For the TPC Front End Electronics (FEE) the control node is a Readout Control Unit (RCU) that communicates to higher layers via Ethernet, using the standard framework DIM (Distributed Information Management). The RCU is equipped with commercial SRAM based FPGAs that will experience errors due to the radiation environment they are operating in. This article will present the implemeted hardware solution for error correction and will focus on the software environment for configuration and controlling of the system.
        Speaker: Mr Dominik Fehlker (University of Bergen)
        Paper
      • 97
        SPIROC (SiPM Integrated Read Out Chip): Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM readout.
        SPIROC is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM readout. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analog memory array with a depth of 16 for each is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analog memory contents (time and charge on 2 gains). The data are then stored in a 4kbytes RAM. A very complex digital part has been integrated to manage all theses features and to transfer the data to the DAQ.
        Speaker: Mr Ludovic Raux (LAL Orsay)
        Paper
        Poster
      • 98
        Status of the Optical Multiplexer Board 9U Prototype
        The Optical Multiplexer Board is one of the elements present in the Read Out chain of the Tile Calorimeter in ATLAS experiment. Due to radiation effects, two optical fibers with the same data are sent from the Front End Boards to this board, which has to decide in real time which one carries good data and pass them to Read Out Driver motherboard for processing. The paper describes the design, tests and status of the first prototype, implemented as a 9U VME64x slave module, including both hardware and firmware aspects. In this last, algorithms for Cyclic Redundancy Code checking are used to make the decision. Besides, the board may be used as a data injector for testing purposes of the Read Out Driver motherboard.
        Speaker: Dr Jose Torres Pais (Universidad de Valencia)
        Paper
      • 99
        System test for the ATLAS Pixel Detector data acquisition
        The ATLAS Pixel Detector is an 80 M channels silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. To verify that the integrated assembly will perform as expected subsequent to installation into the experimental area, a fraction (10%) of the detector and the requisite ancillary services has been assembled and operated in a laboratory setting. We refer to this as system testing, and results from these tests will be presented. The talk will illustrate all the aspects of the system test, including the detector control and safety system, the monitoring system and the DAQ system, the data base technologies used to store the configuration and condition data, the techniques for calibrating the detector and the analysis of noise tests and cosmic data.
        Speaker: Nathan Triplett
        Paper
      • 100
        The ATLAS Level-1 Muon to Central Trigger Processor Interface
        The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing, the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six pT thresholds. This multiplicity value is then sent to the CTP, where it is used together with the input from the Calorimeter trigger to take the final Level-1 decision. In addition the MUCTPI provides data to the Level-2 trigger and to the data acquisition (DAQ) system for events selected at Level-1. This information is used to define regions of interest (RoIs) that drive the Level-2 muon-trigger processing. The MUCTPI system consists of a 9U VME64x chassis with a special backplane and 18 custom designed modules. Each of the 16 octant modules (MIOCT) receives and processes the muon candidate data from 13 sectors of the muon trigger detectors. It calculates the local muon candidate multiplicities and avoids double counting of muon tracks detected in overlapping sectors of an octant. The MIBAK backplane sums the multiplicity values of all MIOCT modules and also provides for readout data transfer and distribution of timing and trigger signals to all the modules in the chassis. The MICTP receives the external timing and triggers signals and sends the final multiplicity value to the CTP. The MIROD module collects information from the MICTP and the MIOCT modules and sends this data after formatting to the Level-2 trigger and the DAQ system via an optical S-LINK interface. The design of the modules is based on state-of-the-art FPGA devices and special attention was paid to low-latency in the data transmission and processing. We present the design and implementation of the final version of the MUCTPI. Results from integration testing with the CTP, the muon trigger system as well as the DAQ and Level-2 systems including data from cosmic ray runs will also be shown.
        Speaker: Mr Stefan Haas (CERN)
        Paper
        Poster
      • 101
        The CMS Pixel FED
        The innermost detector of the CMS Experiment consists of 60 million silicon pixels. The hit data has to be read out and must be digitized, synchronized, formatted and transferred over the S-Link to the final CMS DAQ. The amount of data can only be handled because the readout chip (ROC) delivers zero-suppressed data above an adjustable threshold for every pixel. The Pixel FED 9U VME module receives an optical analogue signal, which is subsequently digitized and processed. The position of the pixel on a module is transmitted with 5 symbols coded in 6 pulse height steps each. The data of 36 inputs from one event build a final event data block. The main challenge is that the information which arrives on the different inputs at the same time can be from different events and can differ up to 16 events depending on the number of hit pixels in past. That is possible because the ROC has a multi event memory and the input data length can be very different. Finally the information will be transferred over the S-Link to the CMS DAQ. Each module must be able to process more than 100 kHz trigger rate or if in trouble to send an alarm signal. The number of inputs is limited by the maximum data transmission rate of the S-Link (640 MB/s) for the expected high luminosity of LHC. The data flow on the module is continuously controlled. Errors are written in an error memory, included in the data stream and if critical sent to the general CMS readout control.
        Speaker: Manfred Pernicka (HEPHY Vienna)
        Paper
        Poster
      • 102
        Track momentum discrimination using cluster width in silicon strip sensors for SLHC.
        The cluster width of a particle crossing a silicon strip (mini strip) detector can be exploited to measure its transverse momentum when the strips are parallel to the B field. This suggests the discrimination of the clusters widths to filter the majority of low momentum particles. Once performed directly on the detectors, such discrimination can be used both for low level trigger (L-1,L-2) and for data reduction. This approach is discussed in the context of a first level trigger based on Tracker for SLHC. The quality of the measurements and their discrimination capability are discussed with respect to the geometry of the sensors and to the detectors layout. Electronics issues and constraints are also reviewed.
        Speaker: Prof. Giuliano Parrini (Dipartimento di Fisica)
        Paper
    • 20:00
      Conference Dinner
  • Friday, 7 September
    • Plenary session P4
      • 103
        ILC Detector R&D
        Although the LHC will explore the energy frontier, and is destined to provide new insights in the fundamental understanding of matter and space-time, it has its intrinsic limitations. The proposed International Linear Collider (ILC) will add significantly to the scientific program of the LHC. This, however, can only be realized if the experimental challenges of the ILC can be overcome. The detectors at the ILC are envisioned to be precision instruments and are a far extrapolation in performance and technology from the current generation experiments. This talk will discuss some of the critical detector R&D that is needed to bring about a successful ILC physics program.
        Speaker: Marcel Demarteau (Fermi National Accelerator Laboratory (FNAL))
        Slides
      • 104
        SYNCHRONIZATION OF THE CMS CATHODE STRIP CHAMBERS
        The synchronization of the trigger and data acquisition systems for the Cathode Strip Chambers (CSCs) in the Compact Muon Solenoid (CMS) detector at CERN is described. To date, asynchronous cosmic ray data have been used to define the protocol and to refine timing algorithms, allowing synchronization to be realized within and between chambers. From this baseline, final synchronization of the CSCs will be readily achieved using data taken with the synchronous beam structure of the Large Hadron Collider. Details regarding the definition, procedures, validation, and performance of the synchronization of the CSCs will be presented.
        Speaker: Dr Gregory Rakness (Univ.of California Los Angeles UCLA)
        Paper
        Slides
      • 105
        DT Sector Collector electronics design and construction
        The CMS detector is equipped with Drift Tubes chambers for muon detection in the barrel region. The Sector Collector modules collect the track segments reconstructed by on-chamber trigger electronics. Data from different chambers are aligned in time and sent to the subsequent reconstruction processors via optical links. Several FPGA devices performing the processing of the data were designed in VHDL, including spy features to monitor the trigger data flow. Prototypes of the boards were operated in the CMS “cosmic challenge”. A test jig was set up with custom hardware and software in order to fully validate final production boards. First experience with installation and running in CMS will be shown.
        Speaker: Dr Luigi Guiducci (Istituto Nazionale di Fisica Nucleare (INFN))
        Paper
        Slides
    • 10:35
      break
    • Parallel session A7 - Systems, Installation and Commissionning 6
      • 106
        The TOTEM electronics system
        TOTEM is an LHC experiment around the same interaction point as CMS. It contains cathode strip chambers (CSC) and gas electron multiplier detectors (GEM) in the CMS cavern and 24 Roman Pots with silicon strip detectors in the LHC tunnel. TOTEM should run both standalone and together with CMS, and should be fully compatible with CMS. All three sub-detectors provide level one trigger building signals and use the same chips: VFAT2 providing both tracking data and fast trigger generation signals, the programmable Coincidence Chip, and the LVDS repeater chip. The same counting room hardware receives and handles both trigger building and tracking data.
        Speaker: Dr Walter Snoeys (CERN)
        Paper
        Slides
      • 107
        The TOTEM Front End Driver, its Components and Applications in the TOTEM Experiment
        The TOTEM Front End Driver or TOTFED receives and handles trigger building and tracking data from the TOTEM detectors, and interfaces to the global trigger and data acquisition systems. The TOTFED is based on the VME64x standard and has deliberately been kept modular, very flexible and programmable to deal with the different TOTEM sub-detectors and possible evolution of the data treatment and trigger algorithms over the duration of the experiment. The main objectives for each unit are to acquire on-detector data from up to 36 optical links, to perform fast data treatment (data reduction, consistency checking, etc...), to transfer to the next level of the system, and to store data on request for slow spy readout via VME64x or USB2.0. The TOTFED is fully compatible with CMS and permits TOTEM to run both standalone and together with CMS. The TOTEM Front End Driver, its components and applications in the TOTEM experiment are presented in this paper.
        Speaker: Mr Gueorgui Antchev (CERN PH-TOT / INRNE-BAS)
        Paper
        Slides
    • Parallel session B7 - Systems, Installation and Commissioning 7
      • 108
        Electronic developments for HADES RPC wall: overview and progress
        This contribution presents the actual status and progress of the electronics developed for the Resistive Plate Chamber detector of HADES. This new detector for the Time of Flight detection system will contain 1000 RPC modules, covering a total active area of around 7 m2. The Front-End electronics consist of custom-made boards that exploit the benefit of the use of commercial components to achieve time resolutions below 100ps. The readout electronics, also custom-made, is a multipurpose board providing a 128-channel Time to Digital Converter (TDC) based on the HPTDC chip.
        Speaker: Mr Alejandro Gil (IFIC (CSIC-UV))
        Paper
        Slides
      • 109
        Low Power Front End for the Optical Module of a Neutrino Underwater Telescope
        A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented. We have used the most recent data coming from simulations of high energy neutrino events produced in a submarine detector in order to define the specifications of the front-end electronics that optimise the detector performance. As a result a new architecture has been defined for the chip that performs the sampling.
        Speaker: Dr Domenico Lo Presti (Catania University - Physics Department and I.N.F.N. Sezione di Catania)
        Paper
        Slides
    • Close out
      • 110
        Close out
    • 12:05
      lunch
    • Tutorial 1
      • 111
        Hardening ASICs against radiation effects
    • 15:00
      break
    • Tutorial 2
      • 112
        Robust ASIC designs for hostile environments
        Speaker: Herman CASIER (IEEE)
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