Jan Dobes (Nuclear Physics Institute, ASCR), Jan Macek (Czech Technical University), Jan Ridky (Institute of Physics, ASCR), Jiri Horejsi (Charles University Prague)
Vaclav VRBA (Institute of Physics, ASCR, Prague)
Several Czech universities and research institutes pursue active research in the field of particle physics. An overview of this research with the stress on experimental and instrumentation aspect will be presented.
Zdenek Dolezal (Charles University Prague)
Dr Daniela Macina (CERN)
The status of the ongoing Large Hadron Collider (LHC) installation is described with particular attention to the Long Straight Sections around the experiments. A summary of the present beam commissioning schedule will be given with some details on the beam conditions during first collisions. The second part of this talk will address in detail the experiment protection system from beam failures...
Luciano Musa (CERN)
ALICE will search for evidence for quark-gluon plasma, the state of matter which is believed to have existed just after the Big Bang, in head-on collisions of lead-ions at the LHC. This requires a very precise tracking capability to record the paths of thousands of particles produced in the collisions. ALICE is therefore built around the largest Time Projection Chamber (TPC) in the world. The...
Prof. Giorgio Spiazzi (University of Padova, Department of Information Engineering - DEI)
Nowadays computing systems comprise a large number of different processing equipment (servers, routers, etc.) with a total power consumption up to some megawatts. In these applications system-level issues like system and component architectures, modeling, control, power management, overall efficiency are of major concern. Different distributed power architectures are firstly reviewed,...
Mr Jiri Gaisler (Gaisler Research AB)
The paper will describe the development and status of radiation- hardened SPARC processors. The SPARC architecture was adopted by the European Space Agency (ESA) in 1992, and has since then been the baseline for most Eropean space missions. SPARC-based processor such as ERC32 are used to control many satellites, including the International Space Station. Newer devices based on the LEON...
Prof. Wayne Luk (Computer Engineering, Imperial College)
The latest field-programmable technology, with enhanced processing, storage and interface capacity, enables the development of powerful and flexible systems that can be customised for specific applications and operating conditions. This presentation describes recent field-programmable systems and tools which have been developed to optimise design quality and designer productivity, and...
Dr Attila RACZ (CERN)
At the time of this paper, all hardware elements of the CMS Data Acquisition System have been installed and commissioned both in the underground and surface areas. This paper describes in detail the infrastructures and the different steps that were necessary from the very beginning when the underground control room was only a building yard to a working system collecting data fragment from...
Jinlong Zhang (Argonne National Laboratory (ANL))
The ATLAS detector is designed to study the proton proton collision at the center of mass energy of 14 TeV with the bunch crossing rate of 40 MHz. In order to reduce this rate down to the level at which the events will be fully reconstructed, the multi-level trigger system is being deployed. The level 1 (LVL1) trigger reduces the rate down to 75 kHz via the custom-built electronics. The...
38. Implementation and performance of the Detector Control System for the electromagnetic calorimeter of the CMS experiment
Jovan Puzovic (VINCA Institute of Nuclear Sciences and Faculty of Physics, Belgrade), Serguei Zelepoukine (ETH Zürich; IHEP Protvino, Moscow)
In this presentation we describe the main design objectives, the detailed specifications and the final layout of the Detector Control System (DCS) for the electromagnetic calorimeter (ECAL) of the CMS experiment. Emphasis is put on the system implementation and specific hardware and software solutions in each of its sub-systems. The latest results from the tests of final prototypes of...
Dr Ralf Spiwoks (CERN)
The ATLAS Level-1 Central Trigger consists of the Muon-to-Central-Trigger- Processor Interface (MUCTPI), the Central Trigger Processor (CTP), and the Timing, Trigger and Control (TTC) partitions of the sub-detectors. The MUCTPI connects the output of the muon trigger system to the CTP. At every bunch crossing it receives information on muon candidates from each of the 208 muon trigger...
Victor Andrei (Kirchhoff-Institut fuer Physik/ Universitaet Heidelberg")
The level-1 calorimeter trigger is a hardware-based system with the goal of identifying high-pt objects within an overall latency of 2.5us. It is composed of a preprocessor system which digitises 7200 analogue input channels, determines the bunch-crossing of the interaction and provides a fine timing and energy calibration; and two subsequent digital processors. The Preprocessor plays...
Dr Stefano Argiro (European Organization for Nuclear Research (CERN))
The experimental conditions and physics goals of LHC experiments set challenging specifications for detectors and their readout electronics. The CMS Electromagnetic Calorimeter (Ecal) is an example of a complex system in which every component needs to be understood in detail in order to ensure the quality of the physics results. In 2006 9 ECAL supermodules were exposed to an electron test...
77. Commissioning of the Jet/Energy-sum and Cluster Processors for the ATLAS Level-1 Calorimeter Trigger System
Richard STALEY (University of Birmingham)
The ATLAS first-level calorimeter trigger is a hardware-based system designed to identify high-pt jets, electron/photon and tau candidates, and to measure total and missing Et. The trigger consists of a preprocessor system which digitises 7200 analogue inputs, and two digital multi-crate processor systems which find jets, measure energy sums, and identify localised energy deposits...
Mr Alexander Ruban (BINP- Bunker Institute of Nucleare Physics, Novosibirsk, Russia)
The CMD-3 Cryogenic Magnet Detector for VEPP-2000 Collider is under construction now. This paper describes hardware part of new DAQ system. The unique features of this system is low EMI, low power and high speed. This is serial-backplane LVDS – media based system. The DAQ system is easy scalable and low-cost due to output to commercially available Fast Ethernet. Special attention is devoted to...
Dr Giulio Villani (STFC Rutherford Appleton Laboratory)
For the ILC physics program, the detectors will need an unprecedented jet energy resolution. For the electromagnetic calorimeter, the use of a highly granular silicon-tungsten calorimeter has been proposed. The status of a silicon readout option, which uses Monolithic Active Pixel Sensors (MAPS), will be presented. This novel design provides extremely fine granularity with integrated...
65. The ATLAS Barrel Level-1 Muon Trigger Sector-Logic/Rx off-detector trigger and acquisition board
Dr Federico Spila (INFN, Sezione di Roma I)
The ATLAS experiment uses a system of three concentric Resistive Plate Chambers (RPC) detector layers for the level-1 muon trigger in the air-core barrel toroid region. The algorithm looks for hit coincidences within different detector layers inside the programmed geometrical road which defines the transverse momentum cut. The on-detector electronics that provides the trigger and detector...
76. Installation and Commissioning the CMS Regional Calorimeter Trigger Hardware into the CMS Level-1 Trigger
Pamela Renee Klabbers (University of Wisconsin - Madison)
The electronics for the Regional Calorimeter Trigger (RCT) of the Compact Muon Solenoid Experiment (CMS) have been produced, tested. The RCT hardware consists of 18 double-sided crates containing custom boards, ASICs, and backplanes. The RCT receives 8 bit energies and a data quality bit from the HCAL and ECAL Trigger Primitive Generators (TPGs) and sends it to the CMS Global Calorimeter...
Prof. K.K. Gan (The Ohio State University)
We study the feasibility of fabricating an opto-link for the SLHC ATLAS silicon tracker based on the current pixel optio-link architecture. The electrical signals between the current pixel modules and the optical modules are transmitted via micro-twisted cables. The optical signals between the optical modules and the data acquisition system are transmitted via rad-hard SIMM fibers fusion...
Dr Costas Fountas (Imperial College)
The CMS Global Calorimeter Trigger(GCT) is the device within the CMS Calorimeter Trigger system which is assigned the tasks of finding and sorting forward, central and tau-jets, sorting isolated and non-isolated electron candidates and reading out all the calorimeter trigger data. The GCT system also provides for a cross-point switch which facilitates the connection between the Calorimeter...
91. Optical absorption in commercial single mode optical fibers induced by gamma rays and complex radiation fields
Dr Thijs Wijnands (CERN)
The optical absorption in 13 SM fibers from 6 manufacturers was studied as a function of dose, dose rate, light power, wavelength and temperature. Two pure Si-core fiber exhibits extreme low radiation induced absorption.
Mr Matthew Stettler (CERN)
The CMS Global Calorimeter Trigger system's HCAL Muon and Quiet bit function is being implemented with a novel processing architecture. This architecture utilizes micro TCA, a modern modular communications standard based on high speed serial links, to implement a processing matrix. This matrix is configurable in both logical functionality and data flow, allowing far greater flexibility...
Daniel Ricci (CERN)
The readout and control optical links, developed for the CMS Tracker and ECAL at CERN, are approaching the final phase of the integration process at LHC Point 5. The individual component parts have been successfully integrated and connected at the innermost distributed patch-panels. Currently, efforts are concentrated on the multi-ribbon optical cables installation and connection to ribbon...
Francois Vasey (CERN)
Marian Krivda (University of Birmingham, UK)
The ALICE trigger system (TRG) consists of a Central Trigger Processor (CTP) and up to 24 Local Trigger Units (LTU) for each subdetector. CTP receives and processes trigger signals from trigger detectors and output from CTP are 3 levels of hardware triggers L0, L1 and L2. 24 trigger detectors are dynamically partitioned into up to 6 independent clusters. The trigger information is...
Mr Giulio Avoni (Istituto Nazionale di Fisica Nucleare (INFN))
This report describes the Selection Crate, designed by INFN for the L0 calorimeter trigger of the LHCb experiment. The Selection Crate is a modular system which consists in 8 Selection Boards (SB) used to select the most energetic clusters detected by the electromagnetic and hadron calorimeters, as well to evaluate other global trigger variables. A SB is equipped with 28 x 1.6 Gbps...
Dr Dave Newbold (University of Bristol / Rutherford Laboratory)
We present a first architectural study of a first-level hardware track trigger for CMS at SLHC. The design of a hardware track trigger at 10^35cm-2s-1 is challenging. A primary constraint on implementation will be power consumption within the detector, in turn driven by the data transmission bandwidth to off-detector electronics. We therefore emphasise the minimisation of the data flow through...
Yasuo Arai (High Energy Accelerator Research Organization (KEK))
We are evaluating SOI (Silicon-On-Insulator) technology for radiation-hard electronics and monolithic radiation sensor applications. The process we used is a 0.15um CMOS, fully-depleted SOI technology developed by OKI Electronics Industry Co. Ltd. This SOI device has two Si layers; one is a thick substrate (handle wafer) which is Czochralski high-resistivity silicon, and another is SOI layer...
Mr Robert Wieland
3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity by combining devices of different technologies. Ultra thin silicon is the base of this...
Mr Ruud Kluit (NIKHEF)
Abstract. The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a candidate to be a good alternative for silicon based pixel detectors. The Gossip chip is being developed to serve as a read-out array for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking...
73. Electronics and Trigger developments for the Diffractive Physics Proposal at 220m from LHC-ATLAS
Mr Jean-François GENAT (LPNHE Paris6)
The instrumentation consists of two sets of Roman Pots installed respectively at 216 and 224m on both sides from the ATLAS IP to measure with precision the position (<10 micrometers) and the timing (< 5 picoseconds) of the two back to back diffracted protons tracks. Each Roman Pot is equipped with several plans of edgeless silicon strip detectors read-out by a new version of the ATLAS SCT...
Eduard Simioni (NIKHEF, Amsterdam, The Netherlands)
The LHCb Outer Tracker is a straw drift detector with a modular design and a total of 55 000 readout channels distributed over a sensitive area of 12 double layers of 6x5 m^2 each. The main electronics readout requirement is the precise (~0.5 ns) drift time measurement at an occupancy of ~4% and 1 MHz readout. A total of 128 channels are read out by one Front-End box. About 450...
Mr Christian Kreidl (Universität Mannheim)
The ASICs required to operate DEPFET matrices - a fast analog switch and a drain current readout chip - are presented.
79. Development of a selftriggered high counting rate ASIC for readout of 2D gas microstrip neutron detectors.
Tomasz Fiutowski (AGH University of Science and Technology, 30-059 Krakow, Poland)
In the frame of the DETNI project a 32-channel ASIC suitable for readout of a novel 2D thermal neutron detector based on a hybrid low-pressure Micro-Strip Gas Chamber and solid 157Gd converter has been developed. Each channel delivers position information, a fast time stamp of 2 ns resolution and signal amplitude proportional to the energy. The time stamp is used for correlating the signals...
Dr Alex Kluge (CERN)
The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 half staves each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8,192 active cells, so that the total number of pixel cells in the SPD is ≈ 10^7. The on-detector read-out is...
Dr Filippo Costa (Department of Physics, University of Bologna, and I.N.F.N Bologna)
The paper presents the test strategy and its results during the installation of the CARLOS end ladder board. This board is able to compress data coming from one Silicon Drift Detector (SDD) front-end electronics and to send them towards the data concentrator card CARLOSrx in counting room via a 800 MBit/s optical link. The paper describes the integration of the CARLOS end ladder boards,...
Dr Christian Schmidt (GSI Darmstadt)
n-XYTER is a 128 channel asynchronous, self triggered, self sparcifying readout ASIC developed as a front-end for neutron scattering detector applications. Due to the novel architecture it has attracted a considerable interest from future heavy ion experiments around the FAIR project. In particular for CBM and PANDA, n-XYTER is currently seen on one hand as the basis and starting point for a...
The innermost part of the ATLAS experiment is a pixel detector, built by around 1750 individual detector modules. To operate the modules, readout electronics and other detector components, a complex power supply and detector control system (DCS) is necessary. This includes a large number of crates, which house the different hardware components as well as a PC net, where the different...
63. VFAT2 : A front-end system on chip providing fast trigger information, digitized data storage and formatting for the charge sensitive readout of multi-channel silicon and gas particle detectors.
Dr Paul Aspell (CERN)
The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC is presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal calibration, intelligent “fast OR” trigger...
4. Development of an ASIC for reading out CCDs at the vertex detector of the International Linear Collider
Mr Peter Murray (STFC)
The Linear Collider Flavour Identification Collaboration is developing sensors and readout electronics suitable for the International Linear Collider vertex detector. In order to achieve high data rates the proposed detector utilises column parallel CCDs, each read out by a custom designed ASIC. The prototype chip (CPR2) has 250 channels of electronics, each with a preamplifier, 5-bit...
Jean-Francois Arguin (LBL (Berkeley))
The ATLAS silicon pixel detector is nearing completion for operation at the Large Hadron Collider at CERN. The ATLAS pixel detector contains approximately 80 million channels and 1744 detector modules. Electronics and module fabrication and testing is complete, as well as system integration of major elements of the pixel detector. The overall status of the ATLAS pixel detector will...
Mr Pierre BARRILLON (Laboratoire de l'Accélérateur Linéaire)
MAROC is the readout chip designed for the ATLAS luminometer made of Roman pots. This ASIC has been realised in SiGe 0.35µm technology and is an evolution of the OPERA_ROC ASIC developed and installed on the OPERA experiment to auto-trigger and readout 64 channels Hamamatsu multi anode PMTs. Its main features are a 100% trigger rate for signal greater than 1/3 photoelectron, a...
Maiike Limper (NIKHEF)
The Barrel and EndCap SCT detectors are installed in the ATLAS cavern. This talk will focus on the installation and first tests of the SCT in-situ. The thermal, electrical and optical services will be reviewed and some of the problems that were encountered during installation will be discussed. The first tests of the SCT in-situ will be described using the calibration scans.. The performance...
Mr Christophe de LA TAILLE (IN2P3/LAL ORSAY)
HARDROC is a complete readout chip in SiGe 0.35µm of the RPCs or GEMs foreseen for a Digital HAdronic CALorimeter (DHCAL) at the ILC. The ASIC integrates 64 channels of • fast low impedance preamplifier with 6bits variable gain (tunable between 0 and 4) • variable shaper (50-150ns) and Track and Hold to provide a multiplexed analog charge output up to 10pC. • variable gain fast...
Dr Heidi Sandaker (CERN)
The Barrel and Endcap SCT detectors have been integrated into the barrel and Endcap TRT detectors. There have been cosmic ray runs for the Barrel and Endcaps in the surface building (SR1) and after installation in the ATLAS cavern. This talk will focus on the most recent results. The procedure for timing in the SCT and TRT for Cosmic runs will be described as well as the procedures to ensure...
Dr Jean-Francois Genat (CNRS/IN2P3/LPNHE)
A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16 deep-analog sampler triggered on input analogue sums, and parallel analog to digital conversion. Tests results of the full chain are reported,...
Georges Blanchot (CERN)
The ATLAS absolute luminosity monitor is composed of 8 roman pots symmetrically located in the LHC tunnel. Each pot contains 23 multi anode photomultiplier tubes, and each one of those is fitted with a front-end assembly called PMF. A PMF provides the high voltage biasing of the tube, the front-end chip and the local readout controller in a very compact arrangement. The 23 PMFs...
Dr John Jones (Princeton University)
We discuss the development and commissioning of a luminosity monitor. It is based on hardware that provides real-time histograms of data from the forward hadronic (HF) calorimeters in CMS. Measuring the total energy deposition and occupancy in these detectors allows us to calculate the relative instantaneous luminosity of the collider on a bunch by bunch basis also useful for machine...
15. Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components
Dr Kostas Kloukinas (CERN), Mr Sandro Bonacini (INPG, CERN)
Most of the microelectronics components developed for the first generation in LHC experiments have been defined and designed with very precise experiment specific goals and are hardly adaptable to other applications. In an effort to cover the needs for generic programmable components often needed in the real world, an industry-compatible Programmable Logic Device (PLD) and an...
56. a low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixels Sensor
Mr Mokrane DAHOUMANE (Laboratoire de physique subatomique et de cosmologie (LPSC))
For CMOS monolithic active pixels sensor readout, we developed a 4 bit very low power analog to digital converter using a double sampling pipelined architecture. The converter consists of a non-resetting sample and hold stage followed by a 2.5 bit sub-ADC and a 2 bit flash. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.3mW at...
Caterina Deplano (INFN Cagliari)
The LHCb Muon System consists of about 122,000 readout channels. It plays a basic role in the first trigger level. The trigger requires 95% efficiency in Muon tracks detection. It is then necessary to reach a system time alignment at the level of about 2 ns. This alignment must be monitored against possible fluctuations due to changes in the detector operating conditions. We describe...
Cristina Fernandez Bedoya (CIEMAT)
Being close to completion of CMS installation, the three levels of the final read-out system of the Drift Tube (DT) chambers is presented. Firstly, the Read Out Boards (ROB), responsible for time digitalization of the signals generated by a charged particle track. Secondly, the Read Out Server (ROS) boards receive data from 25 ROB channels through a 240 Mbps copper link and perform data...
Paulo Moreira (CERN)
The future upgrade of the LHC accelerator, the SLHC, will increase the beam luminosity by a factor of ten leading to a corresponding growth of the amounts of data to be treated by the data transmission and acquisition systems. The development of the GBT ASIC addresses this issue providing a means to increase the bandwidth available to transmit the data to and from the counting room. The GBT...
Dr Michael Campbell (CERN)
Hybrid pixel detectors provide unrivalled pattern recognition capabilities at LHC vertex detectors. Further reducing the material budget is of crucial importance among the many challenges which must be addressed by the vertex systems at SLHC. We propose a two stage front-end pixel readout architecture whereby the discrimination is performed on the sum of the total charge deposited in...
Dr Jianhui Gu (The Ohio State University)
Details of the Cathode Strip Chamber (CSC) Data Acquisition (DAQ) system for the CMS experiment at the LHC will be described. The CSC system is large, consisting of 218K cathode channels and 183K anode channels. This leads to a substantial data rate of ~1.5GByte/s at LHC design luminosity (1034cm-2s-1) and the CMS first level trigger (L1A) rate of 100KHz. The DAQ system consists...
Dr Takuya Sugimoto (Nagoya University)
We will report on the ATLAS commissioning run from the view point of the Thin Gap Chamber (TGC), which is the ATLAS end cap muon trigger detector. So far, a half of TGC chambers with on-detector electronics have been already installed to the ATLAS cavern. To integrate all sub-detectors before the physics run starting from early 2008, the global commissioning run together with other...
Mr Peter Goettlicher (Deutsches Elektronen Synchrotron (DESY))
The detector development for the ILC experiments is driven by the bunch structure of the accelerator, short trains with long empty intervals, and high granularity of the detector. This requires the electronics to be integrated into the active detector volume. This talk exemplifies the concept for the electronics aiming for mechanical compactness through the CALICE-calorimeter. ASIC's nearby...
Mr Peter Phillips
The ATLAS SCT (semiconductor tracker) comprises 2112 barrel modules mounted on four concentric barrels of length 1.8m and up to 1m diameter, and 1976 endcap modules supported by a series of 9 wheels at each end of the barrel. Each module is powered by its own independent, floating low and high voltage power supplies, referenced to ground at the detector shield. Correspondingly each...
Dr Bohuslav Palan (Institute of Physics), Mr Ivan Hruska (Institute of Physics)
The Tile Calorimeter front-end electronics of the ATLAS detector is powered by 256 custom-made low voltage power supplies (LVPS) called LVBOX. Each LVBOX contains eight 150W DC/DC single-output modules transforming 200VDC input into various independent low voltage outputs (+3.3V, +/-5V, +/-15V). A local control and communication board using ELMB permits to monitor behavioral...
Dr Sergei Lusin (Fermilab)
The low voltage system for the on-detector electronics of the CMS Experiment comprises 12090 channels of low voltage power supplies, requiring 1182 KVA of power at the entrance to the CMS facility at CERN. The severe radiation environment inside the CMS experimental cavern combined with an ambient magnetic field reaching up to 1.3 kGauss at the detector periphery severely limit the...
Dr Simone Paoletti (INFN sezione di Firenze)
The power supply system of the silicon strip tracker of the CMS experiment provides HV bias and LV power to the 15 thousand silicon modules comprising the detector, arranged into 1944 "power groups" and 256 "control rings". Around 1200 power supply modules, disposed on 29 racks, operate in a "hostile" radiation and magnetic field environment, 10 m away from the beam crossing region. They...
Marc Weber (Rutherford Appleton Laboratory)
Current silicon detector systems power each detector module independently. For large-scale detectors like the LHC trackers, tens of thousands of cables are needed to power the front-end electronics. At the price of added material, the conventional independent powering is just manageable. For the SLHC trackers, with a five- to ten-fold increase in the number of electronic channels and increased...
Dr Giulio Villani (Rutherford Appleton Laboratory)
Serial powering of silicon sensors will reduce the volume of power cables, the passive material and power losses in cables of future silicon trackers by large factors. These benefits are crucial for silicon tracking at the Super-LHC. Noise performance and grounding and shielding of densely packaged modules are key challenges for serial powering. We extended our studies with six ATLAS...
Dr Masatosi Imori (The university of Tokyo)
A low voltage power supply provides the regulated output voltage of a few volts from the supply voltage around 48 V. The low voltage power supply incorporates a ceramic transformer which utilizes piezoelectric effect to convert voltage. The ceramic transformer isolates the secondary from the primary, thus providing the ground isolation between the supply and the output voltages. The ceramic...
58. High Radiation Resistant DC-DC Converter Regulators for use in Magnetic fields for LHC High Luminosity Silicon Tracker
Dr Satish Dhawan (Yale University)
We have found at least one commercial Buck regulator with integrated inductor fabricated with 0.25µm CMOS technology. This device was exposed to a Cobalt 60 source at BNL; there was negligible effect to 100 mega rad dosage (when the exposure was terminated). System implementation issues are being evaluated.
Mr Stefano Michelis (CERN-PH/MIC)
In view of a power distribution scheme compatible with the requirements of future trackers in SLHC, we are evaluating the feasibility of on-board inductor based DC-DC step-down conversion. Such converter should be integrated and capable of operating in radiation environments and magnetic field. We present results concerning the choice of the CMOS technology for the integrated circuit, the...
Mr Alberto Valero Biot (Instituto de Fisica Corpuscular (IFIC) UV-CSIC)
TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The Read-Out Driver (ROD) is the main component of the TileCal back-end electronics. The ROD is a VME 64x 9u board with multiple programmable devices which requires a complete set of firmware. This paper describes the firmware and functionalities of all these programmable devices, especially the DSP...
Dr David Cussans (H.H. Wills Physics Laboratory)
ILC not a triggered experiment, but during detector development it may be useful to operate in a triggered mode. A Trigger/Tagging Logic Unit (TLU) is described which allows triggered operation, with option of smooth transition to triggerless, data-driven mode. The TLU is being developed as part of the EUDET programme to develop test-beam infrastructure for ILC detector development.
Mr Ricardo Marco (IFIC-Instituto de Física Corpuscular, Universidad de Valenca-CSIC, Valencia, Spain)
A portable readout system for micro-strip silicon sensors has been developed. The system uses an analogue pipelined readout chip, which was developed for the LHC experiments. The system will be used to characterise the properties of both non-irradiated and irradiated micro-strip sensors. Heavily irradiated sensors will be operated at the Super LHC. The system hardware has two main...
42. Calibration and performance tests of the Very-Front-End electronics for the CMS electromagnetic calorimeter
Jan Blaha (Institut de Physique Nucleaire de Lyon (IPNL))
The Very-Front-End electronics processing signal from photodetectors of the CMS electromagnetic calorimeter, have been put through extensive test program to guarantee functionality and reliability. The final characteristics of the VFE boards designed for the calorimeter barrel and endcaps are resented. The results, which have been also verified during test beam at CERN, confirm the high...
Dr Costa Filippo (Department of Physics, University of Bologna, and I.N.F.N Bologna)
The data concentrator card CARLOSrx is a readout board developed for the ALICE ITS Silicon Drift Detector (SDD) experiment held at CERN. CARLOSrx is a 9Ux400 mm VME board, containing 4 FPGAs with the purpose of processing data coming from 12 SDD detectors and sending them to a computer running the DATE software. Twentyfour boards are installed for SDD. We have implemented and tested a new...
The paper describes a novel approach to detect particles by means of an integrated device susceptible to latchup effects; it is proposed as a powerful means of achieving the precise detection and positioning of a broad range of particles with a micrometer spatial resolution. The cell is designed using state-of-the-art AMS 0.35 micron BiCOMS technology. We show the design of a mixed-mode...
Dr Alessandro Gabrielli (INFN & Physic Department of Bologna University Viale Berti Pichat 6/2 40127 Bologna Italy)
The device described in the paper is built up of a bidimensional matrix of MAPS, already designed and fabricated in the past by the SLIM5 Collaboration, and of an off-pixel digital readout sparsification. The readout logic is based on std-cells and implements an optimised token-like technique. It is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for...
Fukun Tang (Enrico Fermi Institute - University of Chicago)
We have proposed using 2" by 2" micro-channel plates (MCP-PMTs) with a novel equal-time anode and with capacitive return path coupling to measure the time-of-flight of relativistic particles, with the goal of being able to construct large-area TOF detectors with a resolution of 1 psec. The proposed front-end customer chip is a time stretcher with 1ps resolution, building with IBM...
Mr FREDERIC DULUCQ (Laboratoire de l Accélérateur Linéaire)
SPIROC (SiPM Integrated Read Out Chip) is the Very Front End ASIC that reads ILC hadronic calorimeter SiPM. It integrates a very complex digital part which performs many functions and manages Acquisition, A/D Conversion and data Read-out. The Acquisition module manages Switched Capacitor Array in which charge and time are stored. This is done by an asynchronous module to meet time...
1. Distribution of the Timing, Trigger and Control Signals in the Endcap Cathode Strip Chamber System at CMS
Mr Mikhail Matveev (Rice University)
This paper presents the implementation of the Timing, Trigger and Control (TTC) signal distribution tree in the Cathode Strip Chamber (CSC) sub-detector of the CMS Experiment at CERN. The key electronic component, the Clock and Control Board (CCB) is described in detail, as well as the transmission of TTC signals from the top of the CSC system down to the front-end boards.
93. ELMB Microcontroller Firmware and SCADA Integration for the LHCb Muon Detector Readout Control System
Dr Rafael Nobrega (INFN Sez. Roma)
The LHCb Muon Detector System will be equipped with about 1400 high efficiency chambers (Multi-Wire Proportional Chambers and Triple-GEM detectors) which will host a total of 7500 front-end boards, each receiving 16 readout channels and having 93 registers for access. A distributed PC network runs the supervision program and allows download of start-up settings and procedures, and upload of...
Takashi Kubota (ICEPP, University of the Tokyo)
For the detector commissioning planned in 2007, a sector assembly of the ATLAS muon-endcap chamber and final test at the surface for the assembled electronics are progressed in CERN intensively. For the test, we built up the DAQ system using test pulse of two types and cosmic ray pulse. So far, 60% of all 320,000 channels have been already tested and most of them were installed into the...
Wieslaw Iwanski (CERN, CH-1211 Geneva 23, Switzerland, INP PAN, Cracow, Poland)
Readout of the front-end electronics of the Absolute Luminosity Monitor is controlled by programmable devices. AlfaR is a local readout controller which reads digitized data with LHC clock and keeps them until validation of the first level trigger. Once validated, data are moved via serial bus to further part of the readout chain supervised by AlfaM chip. This global readout controller...
Dr Jan Troska (CERN)
The Timing, Trigger and Control (TTC) distribution system must ensure high-quality clocking of the CMS experiment to allow the physics potential of the LHC machine to be fully exploited. This key system provides the synchronization tools – bunch clock, first level Triggers and fast commands – that enable all sub-detector systems to take data for the same LHC collision. The challenges of...
Mr Enrico Pozzati (Università di Pavia)
In this work deep N-well CMOS monolithic active pixel sensors (DNW-MAPS) are presented as an alternative approach to signal processing in high energy physics experiments. Based on different resolution constraints, some prototype MAPS, suitable for applications requiring different detector pitch, have been developed and fabricated in 90 nm and 130 nm triple well CMOS technologies....
Andrei Dorokhov (IPHC)
High precision particle tracking and imaging applications require position sensitive detectors with high granularity, good radiation tolerance, low material budget, fast read-out and low power dissipation. Monolithic Active Pixel Sensors (MAPS) fabricated in a standard microelectronic technology provide an attractive solution for these demanding applications. The signal-to-noise...
Dr Alessandro Gabrielli (INFN Sezione di Bologna and Bologna University- Physics Department)
The up-to-date pixel detectors applied to HEP in LHC experiments implement 2D matrixes of sensitive elements that are basically readout via token-based techniques, according to external trigger signals. As the readout time is one of the drawbacks of large matrix devices, because it implies long detector dead times, here it is described a novel readout architecture of pixel devices, which...
Dr Filippo Maria Giorgi (INFN Bologna & Università degli studi di Bologna)
Development, realization and test of an electronic data acquisition-board for the NEMO (NEutrino Mediterranean Observatory) collaboration are described in this work. The collaboration is involved in R&D for the construction of a deep underwater km^3 scale Cherenkov neutrino telescope in the Mediterranean sea. Thousands of optical modules are equipped with a photo multiplier tube and an...
Mr Petr Masek (FEE CVUT Prague, Czech Republic)
A novel read-out (R/O) device based on universal series bus (USB1.0) for spectroscopy data acquisition (DAQ) together with software controlling analog-to-digital converters (type of Canberra, model 8715) will be presented. The interface exploiting the USB1.0 standard has two advantages: USB1.0 is spread out on all platforms and almost computers are equipped with this communication port; and,...
23. Results and Consequences of Magnet Test and Cosmic Challenge for the CMS Barrel Muon Alignment System
Dr Géza Székely (MTA Atomki, Hungary)
In the last year – as part of the CMS test called Magnet Test and Cosmic Challenge (MTCC) - about 25% of the full CMS Barrel Muon Alignment System was built and operated. The configuration enabled us to test all the elements of the system and its function under real conditions. In the paper the setup –including the read-out and control- is described and the first preliminary results are...
Mr Julien Fleury (LAL - Orsay)
This abstract describes the new front end ASIC designed for the silicon tungsten electromagnetic calorimeter called SKIROC. This new chip embeds the main features required for the ILC final detector.
Mr Dominik Fehlker (University of Bergen)
The Time Projection Chamber (TPC) is one of the sub-detectors of the ALICE detector that is currently being commissioned as a part of the Large Hadron Collider (LHC) at CERN. The Detector Control System (DCS) is used for control and monitoring of the system. For the TPC Front End Electronics (FEE) the control node is a Readout Control Unit (RCU) that communicates to higher layers via...
29. SPIROC (SiPM Integrated Read Out Chip): Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM readout.
Mr Ludovic Raux (LAL Orsay)
SPIROC is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM readout. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows...
Dr Jose Torres Pais (Universidad de Valencia)
The Optical Multiplexer Board is one of the elements present in the Read Out chain of the Tile Calorimeter in ATLAS experiment. Due to radiation effects, two optical fibers with the same data are sent from the Front End Boards to this board, which has to decide in real time which one carries good data and pass them to Read Out Driver motherboard for processing. The paper describes the...
The ATLAS Pixel Detector is an 80 M channels silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. To verify that the integrated assembly will perform as expected subsequent to installation into the experimental area, a fraction (10%) of the detector and the requisite ancillary services has been assembled and operated in a...
Mr Stefan Haas (CERN)
The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing, the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six pT thresholds. This multiplicity...
Manfred Pernicka (HEPHY Vienna)
The innermost detector of the CMS Experiment consists of 60 million silicon pixels. The hit data has to be read out and must be digitized, synchronized, formatted and transferred over the S-Link to the final CMS DAQ. The amount of data can only be handled because the readout chip (ROC) delivers zero-suppressed data above an adjustable threshold for every pixel. The Pixel FED 9U VME module...
Prof. Giuliano Parrini (Dipartimento di Fisica)
The cluster width of a particle crossing a silicon strip (mini strip) detector can be exploited to measure its transverse momentum when the strips are parallel to the B field. This suggests the discrimination of the clusters widths to filter the majority of low momentum particles. Once performed directly on the detectors, such discrimination can be used both for low level trigger (L-1,L-2)...
Marcel Demarteau (Fermi National Accelerator Laboratory (FNAL))
Although the LHC will explore the energy frontier, and is destined to provide new insights in the fundamental understanding of matter and space-time, it has its intrinsic limitations. The proposed International Linear Collider (ILC) will add significantly to the scientific program of the LHC. This, however, can only be realized if the experimental challenges of the ILC can be overcome....
Dr Gregory Rakness (Univ.of California Los Angeles UCLA)
The synchronization of the trigger and data acquisition systems for the Cathode Strip Chambers (CSCs) in the Compact Muon Solenoid (CMS) detector at CERN is described. To date, asynchronous cosmic ray data have been used to define the protocol and to refine timing algorithms, allowing synchronization to be realized within and between chambers. From this baseline, final synchronization of the...
Dr Luigi Guiducci (Istituto Nazionale di Fisica Nucleare (INFN))
The CMS detector is equipped with Drift Tubes chambers for muon detection in the barrel region. The Sector Collector modules collect the track segments reconstructed by on-chamber trigger electronics. Data from different chambers are aligned in time and sent to the subsequent reconstruction processors via optical links. Several FPGA devices performing the processing of the data were...
Mr Alejandro Gil (IFIC (CSIC-UV))
This contribution presents the actual status and progress of the electronics developed for the Resistive Plate Chamber detector of HADES. This new detector for the Time of Flight detection system will contain 1000 RPC modules, covering a total active area of around 7 m2. The Front-End electronics consist of custom-made boards that exploit the benefit of the use of commercial...
Dr Walter Snoeys (CERN)
TOTEM is an LHC experiment around the same interaction point as CMS. It contains cathode strip chambers (CSC) and gas electron multiplier detectors (GEM) in the CMS cavern and 24 Roman Pots with silicon strip detectors in the LHC tunnel. TOTEM should run both standalone and together with CMS, and should be fully compatible with CMS. All three sub-detectors provide level one trigger building...
Dr Domenico Lo Presti (Catania University - Physics Department and I.N.F.N. Sezione di Catania)
A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented. We have used the most recent data coming from simulations of high...
Mr Gueorgui Antchev (CERN PH-TOT / INRNE-BAS)
The TOTEM Front End Driver or TOTFED receives and handles trigger building and tracking data from the TOTEM detectors, and interfaces to the global trigger and data acquisition systems. The TOTFED is based on the VME64x standard and has deliberately been kept modular, very flexible and programmable to deal with the different TOTEM sub-detectors and possible evolution of the data treatment and...
Dr Federico Faccio (CERN)
Application-Specific Integrated Circuits (ASICs) designed for application in LHC experiments have to operate reliably in a severe radiation environment. This lecture will introduce the main reasons for failure of CMOS circuits in such environment, and how the sensitivity to radiation effects has evolved with the constant decrease of lithographic dimensions in CMOS manufacturing processes....