3–7 Sept 2007
Prague
Europe/Zurich timezone

Distribution of the Timing, Trigger and Control Signals in the Endcap Cathode Strip Chamber System at CMS

6 Sept 2007, 16:45
1h 15m
Prague

Prague

Czech Republic

Speaker

Mr Mikhail Matveev (Rice University)

Description

This paper presents the implementation of the Timing, Trigger and Control (TTC) signal distribution tree in the Cathode Strip Chamber (CSC) sub-detector of the CMS Experiment at CERN. The key electronic component, the Clock and Control Board (CCB) is described in detail, as well as the transmission of TTC signals from the top of the CSC system down to the front-end boards.

Summary

The Cathode Strip Chamber (CSC) sub-detector currently being commissioned
at CERN comprises 468 six-layer multi-wire proportional chambers arranged in
four stations in the Endcap regions of the CMS. The goal of the CSC system is
to provide muon identification, triggering and momentum measurement. The
CSC electronic system consists of: (1) on-chamber mounted anode and
cathode front-end boards; (2) Trigger and DAQ boards in sixty 9U crates on the
periphery of the return yoke of the CMS; and (3) one Track Finder (TF) and four
Front-End Driver 9U crates located in the underground counting room. In total,
the timing, trigger and command information must be distributed to more than
3500 electronic boards in the entire CSC system.

The top component of the TTC distribution tree within the CSC system is the
Clock and Control Board (CCB). It resides in the middle of the peripheral and TF
crates and carries the TTCrq mezzanine board with the TTCrx and QPLL ASICs.
The TTC clock, Level 1 Trigger and synchronization commands are extracted
from the TTCrx ASIC. In local mode the CCB may generate these signals from
its internal sources under the VME control. The 40MHz and 80MHz clocks from
the QPLL ASIC are transmitted to other boards in the peripheral and TF crates
over custom backplane using individual LVDS lines of the same length while the
commands are distributed via GTLP bus. Further TTC signal distribution to on-
chamber anode and cathode front-end boards is provided from the Trigger and
Data Acquisition Motherboards using the LVDS links.

We describe in detail the  CCB functionality and operating modes as well as

implementation of the TTC and Trigger Control transmission paths throughout
the CSC system. Recent results of the slice and commissioning tests will also be
presented

Primary authors

Mr Frank Geurts (Fermi National Accelerator Laboratory) Mr Mikhail Matveev (Rice University) Mr Paul Padley (Rice University)

Presentation materials