Dr
Kostas Kloukinas
(CERN), Mr
Sandro Bonacini
(INPG, CERN)
05/09/2007, 16:20
Oral
Most of the microelectronics components developed for the first generation in
LHC experiments have been defined and designed with very precise experiment
specific goals and are hardly adaptable to other applications. In an effort to
cover the needs for generic programmable components often needed in the real
world, an industry-compatible Programmable Logic Device (PLD) and an...
Mr
Mokrane DAHOUMANE
(Laboratoire de physique subatomique et de cosmologie (LPSC))
05/09/2007, 16:45
Oral
For CMOS monolithic active pixels sensor readout, we developed a 4 bit very
low power analog to digital converter using a double sampling pipelined
architecture. The converter consists of a non-resetting sample and hold stage
followed by a 2.5 bit sub-ADC and a 2 bit flash. This prototype consists of 4 ADC
double-channels; each one is sampling at 50MS/s and dissipates only 2.3mW at...
Paulo Moreira
(CERN)
05/09/2007, 17:10
Oral
The future upgrade of the LHC accelerator, the SLHC, will increase the beam luminosity by a factor of ten leading to a corresponding growth of the amounts of data to be treated by the data transmission and acquisition systems. The development of the GBT ASIC addresses this issue providing a means to increase the bandwidth available to transmit the data to and from the counting room. The GBT...
Dr
Michael Campbell
(CERN)
05/09/2007, 17:35
Oral
Hybrid pixel detectors provide unrivalled pattern recognition capabilities at LHC
vertex detectors. Further reducing the material budget is of crucial importance
among the many challenges which must be addressed by the vertex systems at
SLHC. We propose a two stage front-end pixel readout architecture whereby
the discrimination is performed on the sum of the total charge deposited in...
