Speakers
Description
Summary
The harsh radiation environment present in the vicinity of high-intensity-beam
particle accelerators, necessary for High Energy Physics (HEP) experiments like
the LHC, requires so far the utilization of custom-designed Application-Specific
Integrated Circuits (ASICs), and forbids instead the exploitation of standard
commercial programmable logic components. Future experiment and upgrades
would benefit from the flexibility of programmable logic covering the need for
small volume applications or where simple logic functions are necessary. Within
this perspective, two industry-compatible radiation-tolerant devices are under
development, respectively a Programmable Logic Device (PLD) and a Field-
Programmable Gate Array (FPGA), targeting two different types of applications.
Studies performed on the radiation effects on most commercial programmable
logic parts have proved them to be often sensitive to both Total-Ionizing Dose
(TID) and Single-Event Upsets (SEUs). SEUs can occur in the user logic and, in
case of SRAM-based devices, also in the configuration registers. When such a
register is corrupted, the user logic can end up being modified, therefore the
functionality can be affected and compromised.
This work focuses on the development of programmable logic designed to be
SEU-robust and TID-tolerant. Our final aim is the creation of an FPGA and a PLD
where SEU insensitivity is built-in, thus not requiring the user to exploit special
technique for SEU protection.
SEU-hardening circuit and layout techniques were employed for the design of a
robust register based on the Dual-Interlocked Cell (DICE). The sensitivity of the
SEU-robust register topology was assessed on a test chip fabricated in a 0.25
micron technology. The circuit proved to be insensitive up to an LET of 79.6
cm2MeV/mg showing minimal sensitivity at higher LETs. The structure of the
register will be described in this paper.
The SEU register was exploited also for the development of a fuse-based PLD.
The configuration fuses are intrinsically hard to SEUs while the user logic is
protected by the SEU-hardened structure. The PLD is a 10-input 8-I/O general
architecture device compatible with most commercial parts. The PLD structure
will be described.
The target FPGA device is an SRAM-based 32×32 logic block matrix which uses
the SEU-robust register for both configuration and user data in order to attain
maximum reprogrammability together with SEU hardness. The FPGA could be
used as a stand-alone chip or as an IP-core. The FPGA fabric under
development will be described.
Both devices can easily be programmed using the same development tools
available for the corresponding commercial parts and adapted to our specific
implementation by a simple post-processing tool. Device programming
considerations will be discussed.
