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4th 28nm Mixed-Signal Design Workshop

11–15 Dec 2023
CERN
Europe/Zurich timezone

Contacts

Contribution List

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  1. 1. Welcome
    Alessandro Caratelli (CERN, EPFL)
    11/12/2023, 09:00
  2. 2. Technology Overview and designer’s guidelines
    Franco Nahuel Bandi (CERN)
    11/12/2023, 09:20
  3. 4. Overview of the 28nm common design platform
    Marco Andorno (CERN)
    11/12/2023, 10:10
  4. 5. Total Ionizing Dose response of the 28nm technlogy
    Giulio Borghello (CERN)
    11/12/2023, 10:55
  5. 32. Analog simulation with Explorer and Assembler
    Helga Dornelas (Cadence)
    11/12/2023, 13:30
  6. 26. Lab session (Analog simulation)
    Helga Dornelas (Cadence)
    11/12/2023, 13:50
  7. 33. Mixed-signal simulation with Xcelium and Virtuoso
    Helga Dornelas (Cadence)
    11/12/2023, 15:30
  8. 28. Lab session (Mixed-signal simulation)
    Helga Dornelas (Cadence)
    11/12/2023, 16:00
  9. 27. Lab session (Mixed-signal simulation)
    Helga Dornelas (Cadence)
    12/12/2023, 09:00
  10. 29. Analog Backend VXL Best Practices
    Philippe Carriere (CERN)
    12/12/2023, 10:45
  11. 34. Lab session (Analog backend)
    Philippe Carriere (CERN)
    12/12/2023, 11:00
  12. 30. Lab session (Analog backend)
    Philippe Carriere (Cadence)
    12/12/2023, 13:30
  13. 42. Abstract generation
    Philippe Carriere (CERN)
    12/12/2023, 15:00
  14. 43. Lab session (Abstract)
    Philippe Carriere (CERN)
    12/12/2023, 15:20
  15. 31. DRC/LVS with PVS
    Philippe Carriere (Cadence)
    12/12/2023, 15:50
  16. 35. Lab session (DRC/LVS with PVS)
    Philippe Carriere (CERN)
    12/12/2023, 16:10
  17. 36. IP block integration (Liberty file and Abstract)
    Marco Andorno (CERN)
    13/12/2023, 09:00
  18. 37. Lab session (Liberty file)
    Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)
    13/12/2023, 09:15
  19. 17. Digital flow introduction
    Erwan Dekhil (Cadence)
    13/12/2023, 10:15

    Main steps of the flow, tools, Flowkit

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  20. 6. Single event effects hardening in digital design
    Alessandro Caratelli (CERN, EPFL)
    13/12/2023, 11:00
  21. 38. Timing constraints and synthesis
    Erwan Dekhil (Cadence)
    13/12/2023, 13:00
  22. 39. Lab session (TMR)
    Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)
    13/12/2023, 15:00
  23. 40. Lab session (Synthesis and LEC)
    Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)
    13/12/2023, 15:30
  24. 18. Block-level implementation
    Erwan Dekhil (Cadence)
    14/12/2023, 09:00

    Synthesis, floorplan

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  25. 19. Block-level implementation
    Erwan Dekhil (Cadence)
    14/12/2023, 10:30

    Placement, clock tree synthesis, routing

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  26. 20. Lab session (Block-level implementation)
    Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)
    14/12/2023, 13:30
  27. 21. Lab session (Block-level implementation)
    Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)
    14/12/2023, 15:00
  28. 22. Hierarchical implementation
    Erwan Dekhil (Cadence)
    15/12/2023, 09:00

    Top level analysis with use of block model, assemble design

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  29. 41. Lab session (Hierarchical implementation)
    Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)
    15/12/2023, 10:30
  30. 23. Signoff
    Erwan Dekhil (Cadence)
    15/12/2023, 13:30

    Timing analysis, power analysis, DRC, LVS

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  31. 25. Lab session (Signoff)
    Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)
    15/12/2023, 15:15
  32. 16. Lab session
    Philippe Carriere (Cadence)
  33. 24. Lab session
    Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)