Speaker
Description
We present and discuss industrially fabricated ion trap chips [1, 2] on the dielectric substrates Fused Silica and Sapphire.
Surface ion trap chips offer a promising platform for the scaling of ion trap quantum computers. We investigate shuttling in the radial direction as element of a scalable architecture [1]. For this, we present chips that are designed to trap ions in two-well potentials in the large separation and in the radial coupling regimes. The chips presented are capable of trapping ions or ion chains in separate rf potential wells. The design parameters of a surface ion trap in the radial coupling regime with fixed ion height and ion-ion distance are investigated. Based on this, we present improved trap designs. We discuss the simulation, design and fabrication challenges involved in creating such chips. The traps are or will be fabricated on single- and multi-layer stacks. The fabrication on multi-layer stacks enables a more complex electrode geometry and therefore more complex scalable ion trap layouts.
The ion traps are fabricated on the dielectric substrates Fused Silica and Sapphire, which are ultra-wide-bandgap materials and therefore promise excellent resilience against UV light and low rf losses. The status of industrial microfabrication on these materials is discussed, with a focus on the challenges of fabrication on different substrate materials and the fabrication of multi-layer stacks.
[1] Ph. Holz, S. Auchter et al., Adv. Quantum Technol. 3, 2000031 (2020)
[2] S. Auchter, C. Axline et al., Quantum Sci. Technol. 7, 035015 (2022)
