2–7 Sept 2012
Hotel Listel Inawashiro, Inawashiro, Japan
Japan timezone

Development of Data-Acquisition Front Ends enabling High-bandwidth Data Handling for X-ray 2D Detectors: A Feasibility Study

4 Sept 2012, 15:20
1h
Hotel Listel Inawashiro, Inawashiro, Japan

Hotel Listel Inawashiro, Inawashiro, Japan

Kawageta, Inawashiro, Fukushima 969-2696
POSTER Data reconstruction and algorithms - Pattern recognision and imaging Poster session

Speaker

Choji Saji (JASRI/SPring-8)

Description

X-ray 2D detectors are indispensable for synchrotron radiation and X-ray free-electron laser experiments such as coherent x-ray imaging, spectroscopies, time-resolved experiments etc. In these experiments, spatial, temporal, or photon energy information are projected onto X-ray 2D detector surface. It is generally accepted that larger pixel number and higher dynamic range will provide clearer information on the sample. These demand high-bandwidth front ends (FEs) for data acquisition (DAQ) system. In the case of SOPHIAS sensor under development at SACLA (SPring-8 Angstrom Compact free electron LAser), each sensor in the final form will have 2 M pixels running at up to 300 Hz, and produces data at upto 20 Gbps. In order to realize the front ends for SOPHIAS as well as other high-bandwidth detectors, a feasibility study has been carried out by using an evaluation board. The board has FPGA with FMC (FPGA mezzanine card) interface in order to support various physical layers of sensor readout modules and DAQ back ends (BEs). In this study, the bandwidth from FPGA to BEs were evaluated for XAUI with SFP+ (Small Form-factor Pluggable plus) physical layer. One of the advantages of XAUI is that it interfaces MAC (Media Access Control) to PHY layer of 10 Gigabit Ethernet (GbE) enabling distributed DAQ system with 10 GbE network. In many photon science applications, scalability from single to many modules is of importance. As a candidate for FEs for small detector system, a compact desktop-type DAQ system based on PCI express bus was evaluated. A FE board with PCI express will be connected to PC, and the data will be transferred to PC storage directly. Measurements of the bandwidth by using the evaluation board indicated successful effective bandwidth of 9 Gbps and 16 Gbps though SFP+ with XAUI and PCI express, respectively. Details of the evaluation scheme will be discussed in the presentation. And our developing sensor connection device, Camera Link FMC, will be reported.

Primary author

Choji Saji (JASRI/SPring-8)

Co-authors

Mitsuhiro Yamaga (JASRI/SPring-8) Ryotaro Tanaka (JASRI/SPring-8) Takaki Hatsui (RIKEN) Takashi Sugimoto (JASRI/SPring-8) Togo Kudo (JASRI/SPring-8) Toru Ohata (JASRI/SPring-8)

Presentation materials