Speaker
Laura Gonella
(Universitaet Bonn (DE))
Description
With the planned upgrades of the LHC for higher than present luminosity, the ATLAS pixel detector will be confronted to higher hit rate. R&D for the inner layers of the future ATLAS pixel detector has started in the direction of smaller feature size CMOS bulk processes, as well as in the direction of the new possibilities offered by 3D integration technologies. In this presentation, a report will be given on 2 different 3D integration techniques for the future pixel readout IC which were followed by the ATLAS pixel collaboration. The first one consists in the drilling of Through Silicon Via (TSV) in a via first approach, with the benefits associated to small aspect ratio and the insertion of the TSV at the pixel level, but also the technical issues of a technology still presenting challenges for the industrial partners. The second one consists in the drilling of the TSV via-last, with a potential for improved module concepts, despite the somewhat coarser technology and the associated reduction in via density. First results from both approaches are now available and will be discussed.
Author
Marlon Barbero
(Bonn University)
