5th 28 nm Mixed-Signal Design Workshop

Contribution List

1. Welcome

Alessandro Caratelli (CERN, EPFL)

08/04/2024, 09:00

Overview of the 28nm technology

2. Technology Overview and designer’s guidelines

Franco Nahuel Bandi (CERN)

08/04/2024, 09:20

Overview of the 28nm technology

4. Overview of the 28nm common design platform

Marco Andorno (CERN)

08/04/2024, 10:10

Overview of the 28nm technology

5. Total Ionizing Dose response of the 28nm technlogy

Giulio Borghello (CERN)

08/04/2024, 10:55

Overview of the 28nm technology

32. Analog simulation with Explorer and Assembler

Helga Dornelas (Cadence)

08/04/2024, 13:30

Analog design

26. Lab session (Analog simulation)

Helga Dornelas (Cadence)

08/04/2024, 13:50

Analog design

33. Mixed-signal simulation with Xcelium and Virtuoso

Helga Dornelas (Cadence)

08/04/2024, 15:30

Mixed-signal design

28. Lab session (Mixed-signal simulation)

Helga Dornelas (Cadence)

08/04/2024, 16:00

Mixed-signal design

27. Lab session (Mixed-signal simulation)

Helga Dornelas (Cadence)

09/04/2024, 09:00

Mixed-signal design

29. Analog Backend VXL Best Practices

Philippe Carriere (CERN)

09/04/2024, 10:45

Analog design

34. Lab session (Analog backend)

Philippe Carriere (CERN)

09/04/2024, 11:00

Analog design

30. Lab session (Analog backend)

Philippe Carriere (Cadence)

09/04/2024, 13:30

Analog design

42. Abstract generation

Philippe Carriere (CERN)

09/04/2024, 15:00

Mixed-signal design

43. Lab session (Abstract)

Philippe Carriere (CERN)

09/04/2024, 15:20

Mixed-signal design

31. DRC/LVS with PVS

Philippe Carriere (Cadence)

09/04/2024, 15:50

Analog design

35. Lab session (DRC/LVS with PVS)

Philippe Carriere (CERN)

09/04/2024, 16:10

Analog design

36. IP block integration (Liberty file and Abstract)

Marco Andorno (CERN)

10/04/2024, 09:00

Mixed-signal design

37. Lab session (Liberty file)

Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

10/04/2024, 09:15

Mixed-signal design

17. Digital flow introduction

Erwan Dekhil (Cadence)

10/04/2024, 10:15

Digital design

Main steps of the flow, tools, Flowkit

6. Single event effects hardening in digital design

Alessandro Caratelli (CERN, EPFL)

10/04/2024, 10:45

Digital design

39. Lab session (TMR)

Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

10/04/2024, 11:30

Digital design

38. Timing constraints and synthesis

Erwan Dekhil (Cadence)

10/04/2024, 13:30

Digital design

40. Lab session (Synthesis and LEC)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

10/04/2024, 15:30

Digital design

18. Block-level implementation

Erwan Dekhil (Cadence)

11/04/2024, 09:00

Digital design

Synthesis, floorplan

19. Block-level implementation

Erwan Dekhil (Cadence)

11/04/2024, 10:30

Digital design

Placement, clock tree synthesis, routing

20. Lab session (Block-level implementation)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

11/04/2024, 13:30

Digital design

21. Lab session (Block-level implementation)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

11/04/2024, 15:00

Digital design

22. Hierarchical implementation

Erwan Dekhil (Cadence)

12/04/2024, 09:00

Digital design

Top level analysis with use of block model, assemble design

41. Lab session (Hierarchical implementation)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

12/04/2024, 10:30

Digital design

23. Signoff

Erwan Dekhil (Cadence)

12/04/2024, 13:30

Digital design

Timing analysis, power analysis, DRC, LVS

25. Lab session (Signoff)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

12/04/2024, 15:15

Digital design

16. Lab session

Philippe Carriere (Cadence)

Analog design

24. Lab session

Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)

Digital design

44. Lab Session (Digital Flow and TMR techniques)

Alessandro Caratelli (CERN, EPFL)

Digital design