Speaker
Description
This work describes a custom electronics board (“PicoTDC board”) developed at INFN Bologna, whose goal is to provide fast timing measurements to generic detectors able to test different front-end electronics using a common FMC interface. The fast timing measurements are achieved using 2 PicoTDC ASICs from CERN, providing 128 channels with 3.05 ps LSB. Design choices and performance of the card are discussed. The results obtained using the PicoTDC board with a FMC card hosting the LIROC chip for the readout of SiPMs and LGADs at a test-beam at the Proton Synchrotron facility at CERN will also be presented.
Summary (500 words)
The PicoTDC board features 2 PicoTDC ASICs from CERN, one Microchip PolarFire FPGA MPF200T and several data interfaces towards a host computer performing configuration and data acquisition. The board houses a 1 Gb/s Ethernet link, two USB-C 3.0 interfaces (FTDI FT601Q and Cypress FX3) and a SFP connector (potentially up to 14 Gb/s). Two high-density FMC connectors provide the 128 differential I/O channels for the TDC. Connectivity to compliant FMC mezzanine hosting the front-end electronics (FMC- PicoTDC Front End Board: FMC-PFEB) is obtained via FPGA-remappable I/O signals. Up to 15 SMA I/Os are available, among which an optional external reference clock can be provided. Differential traces on the board (from FMC to PicoTDC input and from PicoTDC to the FPGA) have been routed with controlled impedance to guarantee the signal integrity, resulting in a 14 layers PCB.
The card was designed to provide:
● a test environment for the development of a Microchip PolarFire FPGA coupled to the PicoTDC ASIC to refine design choices of a new 256 channels TDC Readout Module for the ALICE TOF detector (to replace existing cards based on HPTDC CERN ASIC);
● a flexible high resolution timing card for laboratory studies with sensors like MRPC, LGAD, CMOS-LGAD and SiPM, testing different front-end solutions. The
card is being used in the context of MRPC R&D (under AIDAInnova EU Project) and ALICE3 R&D; ● a laboratory card to study and optimize data readout links to host computers;
● a useful “open tool” to engage master students in various activities, such as firmware and software design, development of test setups for high precision timing measurements, and laboratory exercises in DAQ courses.
The first data link implementation was made with the IPBUS protocol on the Ethernet link, both for configuration and data readout. Firmware for the USB interface (FTDI) is also under development: a 2 Gb/s data throughput has been already achieved. In both cases software was developed on a Linux AlmaLinux 9 host.
The PicoTDC performance was tested stimulating two PicoTDC channels via a custom FMC adapter with a LVDS pulse generated by a SkyWorks SI5341-B (at 100 KHz) and a controlled delay line using a Colby electromagnetic trombone. The single channel time resolution is about 2.90 ps, confirming the expected performance and the good design choices.
The first implementation of a FMC-PFEB is based on 64-channel Weeroc LIROC ASIC, specifically optimized to amplify and discriminate signals received from SiPMs. This setup is being used at a test-beam at CERN PS in May and July 2024 and results of the performance of the card in that DAQ context will be reported.
Results so far proved that the PicoTDC board is a viable and flexible instrument for performing fast timing measurements testing different front-end electronics. Future plans include, besides intensive use at on-going test beams in the context of AIDAInnova and ALICE3 R&D, developments of other generic FMC-PFEB cards (LVDS - Sub-LVDS adapters, etc.), implementation of the data transfer over the optical link and irradiation tests of some components.
