Speaker
Description
Abstract
In this presentation, we will explore the critical role of on-chip ESD protection in advanced semiconductor processes. Starting with an introduction to ESD events and their potential to catastrophically damage semiconductor circuits, we will delve into the strategies employed to mitigate these risks. Traditional ESD protection methods, while sometimes effective, often introduce challenges such as excessive capacitance, large area consumption for power clamps, and inflexible design constraints.
We will then shift focus to a local clamp approach, which utilizes ESD clamps inside the I/Os to offer greater design flexibility, significant overall area savings, reduced leakage, and minimized parasitic capacitance, all while ensuring robust protection for thin oxide transistors. This approach's effectiveness will be demonstrated through examples in advanced semiconductor processes, including 28nm and 22nm CMOS, as well as 16nm to 3nm FinFET technologies.
For the particle physics research at CERN, electronics must be designed with greater radiation tolerance. Traditional ESD clamps frequently rely on thick oxide transistors which cause excessive leakage after radiation. Over the past few years, Sofics has successfully delivered ESD clamps and I/O circuits across several process nodes to CERN, contributing to the design of radiation-hardened electronics and sensors.
Join us to gain insights into the latest advancements in ESD protection and learn how Sofics is pushing the boundaries of semiconductor reliability and performance.
