Speaker
Description
In large-scale physical experiments, the experimental devices are widely distributed in space and have a large number of end nodes. To ensure that all components can work synchronously and complete precise correlation measurement at different positions, the clocks of all nodes are required to be from the same source and to achieve automatic phase synchronization, as well as the fusion transmission of clock, data, and commands. The existing techniques in this direction are highly dependent on high-end and special programmable FPGA devices, and based on the requirements and characteristics of large-scale physical experiment signal readout, front-end electronics widely use customized application-specific integrated circuits (ASICs), so the current clock interface devices in this direction cannot achieve high integration with front-end ASICs. To solve the above problem, this work focuses on the research of high-precision clock distribution and synchronization ASIC techniques, overcomes the key problems such as delay fixing of the high-speed transceiver circuit and fine adjustment of the clock phase, and develops a series of ASIC design techniques. On the basis of the method research, the design and fabrication of the prototype chip have been completed. The chip is currently undergoing packaging, and testing will commence shortly. The precision of the clock synchronization is designed to be better than 50 ps and the period jitter is expected to be better than 10 ps in RMS.
