Speaker
Description
An asynchronous read-out architecture was developed for the MALTA family of Pixel detectors in Tower 180 nm as an alternative to well established column-drain architecture by means of a self-generating reference pulse in groups of 8x2 pixels without the distribution of a clock over the matrix, a power consumption smaller than 80 uW/cm2 and a hit rate capability larger than 1 GSps. The aim of this proposal is to develop this architecture further to reach hit rates above 100 MHit/cm2, radiation hardness better than 3e15 n/cm2, and on-chip time tagging below 1 ns. Hit rate capability and radiation hardness have been evaluated with the MALTA and MALTA2 prototypes. Sub-nanosecond timing resolution is being evaluated with the latest prototype, Mini-MALTA3, that includes an upgraded synchronization memory that runs at a clock speed of 1.28 GHz generated by an on-chip PLL. This proposal considers to explore the limit of Tower 180 nm imaging process on which the designs are available to design a prototype with a matrix larger than 2x2 cm2 with output data protocol compatible with the state of the art optical transveivers. This proposal has an potential application for beam tests across the DRD3 community.
| Type of presentation (in-person/online) | in-person presentation |
|---|---|
| Type of presentation (scientific results or project proposal) | project proposal for future work |
