Speaker
Description
The Medipix4 ASIC is the latest hybrid pixel detector in the Medipix family, developed using commercial 130nm CMOS technology for high-rate spectroscopic X-ray imaging. Like Timepix4, the Medipix4 chip features a four-side buttable design, enabling seamless large-area tiling via Through-Silicon Vias (TSV). Alternatively, the chip can be interfaced via top and bottom peripheral wirebonding, achieving a two-side buttable configuration. The chip consists of a 320 × 320 pixel matrix with a 75 $\mu$m pitch in Fine Pitch Mode (FPM), or a 160 × 160 pixel matrix with a 150 $\mu$m pitch in Spectroscopic Mode (SM). The SM is specifically optimized for high-Z sensor materials.
In Fine Pitch Mode, the chip supports two effective thresholds, whereas in Spectroscopic Mode, it supports up to eight thresholds. The chip can operate in Single Pixel Mode (SPM) or Charge Summing Mode (CSM), the latter of which corrects for charge-sharing effects among neighboring pixels. Each 75 $\mu$m pixel is equipped with two 12-bit counters, which can be used in continuous read/write mode (CRW) or configured for 1-bit, 2-bit, 12-bit, or 24-bit counter operation in sequential read/write mode (SRW). Additionally, threshold window discrimination and a pileup filter are available for enhanced performance. The Medipix4 chip operates in a highly configurable frame-based readout mode. It can be read out using up to 16 high-speed links, each capable of 640 Mbps, achieving 8.3k frames per second (fps) in 12-bit counter mode.
In this presentation, we will provide an overview of the Medipix4 architecture and its operating principles, alongside initial characterization results, including energy resolution estimation and rate sustainability.
| Workshop topics | Front-end electronics and readout |
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