Speaker
Description
X-ray hyperspectral detectors using charge-integrating pixels detect individual photons at frame rates generally higher than one kilo frames per second (kfps). Owing to the slower analog processing, they enable spectroscopic analysis with sharper energy resolution, typically better than 1 keV FWHM.
CITIUS is a recently introduced large-area, direct-detection X-ray detector, of which the development was led by RIKEN SPring-8 Center (Japan). It integrates a 650 µm-thick silicon sensor with a CMOS readout chip comprising a matrix of (728×384) integrating-type pixels with 72.6 µm pitch. In the spectro-imaging operating mode, CITIUS operates as a hyperspectral detector at 26.1 kfps to detect isolated photons in each acquired frame. Under optimal conditions, CITIUS achieves an energy resolution of 380 eV FWHM (full width half maximum of photo peak) at 8.0 keV for events where the charge released is confined to a single pixel. Additionally, an improved energy resolution of 220 eV FWHM at 5.9 keV has been demonstrated at the cost of a reduced frame rate of 2.2 kfps, using an eight-frame sampling mode. Note that these results were obtained at room temperature. The combination of high frame rate, large detector area, room temperature operation, and good energy resolution makes CITIUS a promising candidate for spectral Computed Tomography (CT), as demonstrated using a laboratory liquid metal-jet X-ray source [1].
A major limitation of hyperspectral detectors using charge-integrating devices is the need to acquire a large number of frames, each containing sparsely distributed photons, to reconstruct spectral information with specialized post-processing procedures. This approach requires high data volumes, large storage capacities, and time-consuming post-processing. To address these limitations, we propose an innovative real-time FPGA-based spectral reconstruction algorithm, implemented for the CITIUS detector in the spectro-imaging mode. This solution ensures real-time data reduction and visualization, significantly enhancing the suitability of CITIUS for spectral CT applications by eliminating extensive post-processing, reducing storage requirements, and shortening acquisition times due to minimized data transfer.
For the CITIUS detector, deducing photon energy requires computation over a 3×3 pixel matrix per event, posing a significant challenge given the data throughput of 7.296 Gpixels/s per module (29.19 GB/s). To enable low-latency and reliable processing, we implemented the spectro-imaging algorithm in Verilog HDL on three custom-developed FPGA cards, which we call Data Framing Boards (DFBs) [2]. Each DFB hosts three Arria10 FPGAs (Intel Corporation, USA): two are dedicated to the calibration of pixel data streams output from CITIUS, and one to the spectro-imaging mode. Preliminary results obtained at 26.1 kfps show strong agreement between the spectra reconstructed by the FPGA and those computed offline by a CPU (Figure 1).
In this presentation, we provide an overview of the implemented algorithm and report on the experimentally validated performance of the real-time spectro-imaging pipeline.
[Figure1.jpg]
Figure 1: Energy spectra measured by X-ray photon event from a Fe55 and a Cd109 radioactive sources. The number of measured frames is 261,000 frames for FPGA and 30,000 frames for CPU. CITIUS detector was operated in the spectro-imaging mode at 26.1 kfps. The sensor temperature was +30 degree Celsius.
References
[1] V. Di Trapani, et.al., presented at iWoRiD 2024
[2] H. Nishino et.al., Nucl. Instrum. Methods Phys. Res. Sect. A, Vol. 1057, p. 168710, (2023)
| Workshop topics | Detector systems |
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