Speaker
Description
Timepix4 [1] is the latest readout chip in the Timepix family of detectors, developed at CERN within the Medipix collaboration. Compared to its predecessor, it offers higher resolution (512 × 448 pixels with a 55 µm pitch) and significantly improved Time-of-Arrival (ToA) performance, with time binning down to 195 ps. Timepix4 is also capable of handling extremely high hit rates — up to 2.5 Ghits/s per chip — transmitted via sixteen serial output lines, each supporting data rates of up to 10 Gbps.
Currently, the primary readout system used with Timepix4 is SPIDR4, developed by Nikhef [2]. While this system excels in high-speed performance for test beams and large-scale experiments, it lacks a user-friendly interface and is not ideally suited for compact laboratory setups or educational environments.
In this contribution, the authors present and discuss the architecture of a proposed compact acquisition system for Timepix4, designed specifically for laboratory measurements, demonstrations, and educational use. The system will support a single Timepix4 chip and is expected to provide a reduced bias voltage range, suitable primarily for silicon sensors. A USB interface is being considered to ensure simple connectivity with laptops or tablets.
The authors also explore strategies to avoid the use of expensive FPGA platforms with high-speed transceivers, while still enabling basic operation of Timepix4. The contribution includes an overview of the system’s planned features and describes the current status of its development.
References:
[1] Llopart, Xavier, et al. "Timepix4, a large area pixel detector readout chip which can be tiled on 4 sides providing sub-200 ps timestamp binning." Journal of Instrumentation 17.01 (2022): C01044.
[2] Online. https://indico.nikhef.nl/event/2243/contributions/5102/attachments/2401/2807/SPIDR4-MF-GP-apr2020.pdf
| Workshop topics | Detector systems |
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