20–24 Jan 2025
CERN
Europe/Zurich timezone
There is a live webcast for this event.

Optimisation of Multi-Qubit Chip Topology

Not scheduled
20m
Pas Perdus and Mezzanine (CERN)

Pas Perdus and Mezzanine

CERN

Speakers

Mr Priyangshu Chatterjee (IIT Kharagpur) Rajatava Mukhopadhyay (TCG Crest)

Description

The poster titled "Optimisation of Multi-Qubit Chip Topology" focuses on designing scalable and efficient architectures for multi-qubit quantum processors. The research highlights superconducting qubits, known for their controllability and role as fundamental units of quantum information in quantum computing. This study emphasises the importance of parameters such as entanglement, quantum error correction, and scalability in multi-qubit chip design. The team proposes a 2D architecture with three qubits arranged in an equilateral triangle and a 3D architecture with four qubits in a tetrahedral structure. These configurations can serve as modular units for larger quantum systems. Future directions include optimising resonator lengths, energy participation ratios, and scaling up the architecture for larger multi-qubit arrays and systems. In high-energy physics, qubit systems are used for quantum simulations complex particle interactions. Thus, an easily scalable multi-qubit chip will definitely be the way forward to complex calculations and simulations of particle collisions at high energies, thus paving the way for its usage in high energy physics in the near future for newer and more exciting discoveries.

Email Address of submitter

rajatava.m@gmail.com

Authors

Prof. B N Dev Mr Priyangshu Chatterjee (IIT Kharagpur) Rajatava Mukhopadhyay (TCG Crest) Dr Snehal Mandal (TCG Crest)

Presentation materials

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