2nd FPGA Developers' Forum (FDF) meeting

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Group Picture

Conclusions

HDL Development Tools

Verification

Algorithm Implementation

Solutions to everyday digital design problems

Sharable HDL cores

Introduction

Hardware Development

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Contributions*

A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine (in session "Algorithm Implementation")

A Reconfigurable FPGA-Based ML Library for Kernel Methods (in session "Algorithm Implementation")

Abstract interface modelling for better genericity and code clarity (in session "Solutions to everyday digital design problems")

Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments (in session "Algorithm Implementation")

Allo: A Python-Embedded Programming Model for Composable Accelerator Design (in session "HDL Development Tools")

Application-Specific Arithmetic Operators with the FloPoCo HDL core generator (in session "HDL Development Tools")

Architecting FPGA for low power Leadership (in session "Hardware Development")

CERN ABT's lazy git workflow for equipment-specific designs (in session "Solutions to everyday digital design problems")

CERN Campus Visits

Chisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators (in session "Algorithm Implementation")

Closing Remarks (in session "Conclusions")

Common Exchange Format for HDL Build Systems (in session "HDL Development Tools")

Customized eFPGAs with FABulous (in session "HDL Development Tools")

Disruptive Efinix Quantum Architecture (in session "Solutions to everyday digital design problems")

Distributed Arithmetic for Real-time Neural Networks on FPGAs (in session "Algorithm Implementation")

Enhancing FPGA Verification by Combining VUnit and UVVM (in session "Verification")

Error-Redundant Implementation of Commercial IP Cores: A Practical Example (in session "Sharable HDL cores")

Exploring Linearity and Temperature Stability in Time-to-Digital Converters (in session "Algorithm Implementation")

FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems (in session "Algorithm Implementation")

Generating memory maps with Cheby and Reksio (in session "HDL Development Tools")

Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage) (in session "Verification")

HDLRegression: A reliable and efficient tool for FPGA regression testing (in session "HDL Development Tools")

High Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing (in session "Verification")

Implementation of Time to Digital Converter on FPGA for high-resolution-performance in Particle Therapy applications (in session "Algorithm Implementation")

Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers (in session "Solutions to everyday digital design problems")

NDK: An open-source framework for high-speed network applications on FPGAs (in session "Sharable HDL cores")

Open Logic – open-source FPGA Standard Library (in session "Sharable HDL cores")

Practical Methods for Functional Verification (in session "Verification")

Python-based, flexible testbench for a spacecraft payload (in session "Verification")

Standardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms (in session "Solutions to everyday digital design problems")

Summary of FDF2025 and Awards (in session "Conclusions")

The future of FPGAs in HEP detectors for FCC and beyond (in session "Introduction")

The new CI4FPGA service at CERN (in session "Solutions to everyday digital design problems")

The PandABlocks framework for flexible run-time configuration of Zynq SoCs (in session "Sharable HDL cores")

Unleashing >100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST (in session "Sharable HDL cores")

Welcome to CERN (in session "Introduction")

Welcome to the 2nd FPGA Developers' Forum (in session "Introduction")

Where Innovation Meets Reliability – FPGA based solutions by Trenz Electronic (in session "Algorithm Implementation")

Why Your Team Should be using VHDL + OSVVM for Verification (in session "Verification")

YosysHQ - Building alternative FPGA toolchains (in session "HDL Development Tools")

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Events scheduled on*

20/05/2025

21/05/2025

22/05/2025

23/05/2025

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