2nd FPGA Developers' Forum (FDF) meeting

Chisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators

21 May 2025, 11:50

30m

500/1-001 - Main Auditorium (CERN)

Algorithm implementation in HDL and HLS Algorithm Implementation

Speaker

Jure Vreča (Jožef Stefan Institute)

Description

Chisel4ml is a tool we developed for generating fast implementations of deeply quantized neural networks to FPGA devices. The tool is implemented in the Chisel Hardware Construction Language, and has a frontend in Python, to enable interfacing with neural network training libraries. We will present basics of the Chisel language and compare chisel4ml against hls4ml. In general, chisel4ml, is able to generate the hardware much faster then high-level synthesis solutions, because it uses structural descriptions of the circuits.