20–23 May 2025
CERN
Europe/Zurich timezone
There is a live webcast for this event.
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Application-Specific Arithmetic Operators with the FloPoCo HDL core generator

22 May 2025, 09:00
30m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
Show room on map
HDL development tools HDL Development Tools

Speaker

Florent de Dinechin (INSA-Lyon)

Description

Software programming languages have trained us to view computing in terms of a handful of operations over a handful of integer and floating-point formats: those supported by general-purpose processors and GPUs. In FPGAs, however, we have the opportunity to design the arithmetic for the application. This is both a qualitative challenge (what is the best way to compute an exponential or an FFT in an FPGA?) and a quantitative one (how many bits are necessary and sufficient on each bus of the hardware?).
Addressing these challenges has been the goal of the open-source FloPoCo project (www.flopoco.org) for 15 years. This talk will demonstrate some of its fancy operators, review some of the methodologies developed for optimizing and testing them, and discuss the challenges and opportunities of HLS in this context. It will also shamelessly advertise our recent book "Application-Specific Arithmetic: Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era".

Talk's Q&A During the talk
Talk duration 20'+10'
Will you be able to present in person? Yes

Authors

Florent de Dinechin (INSA-Lyon) Prof. Martin Kumm (Fulda University of Applied Science)

Presentation materials