Speaker
Description
HDLRegression was developed to provide a reliable, efficient tool for regression testing of maintenance testbenches for UVVM and other FPGA project testbenches. It simplifies simulations with minimal changes—just a single comment in the testbench entity—making it easy to integrate into existing projects.
One big advantage is its independence from any specific verification framework, enabling use with UVVM, OSVVM, VUnit, or any other in-house tools for maximum flexibility.
As FPGA designs grow more complex, numerous tests are needed to verify functionality. HDLRegression addresses this with efficient, customisable test execution and a structured testing environment where results are easily accessible.
By offering reliable and efficient regression testing, HDLRegression improves testing processes, reduces complexity, and increases reliability in FPGA projects.
| Talk's Q&A | End of talk |
|---|---|
| Talk duration | 20'+10' |
| Will you be able to present in person? | No |
