Software programming languages have trained us to view computing in terms of a handful of operations over a handful of integer and floating-point formats: those supported by general-purpose processors and GPUs. In FPGAs, however, we have the opportunity to design the arithmetic for the application. This is both a qualitative challenge (what is the best way to compute an exponential or an FFT...
FABulous is an eFPGA (embedded FPGA) framework comprising a full ecosystem for specifying, simulating, emulating and implementing FPGA ASIC macros as well as for providing the corresponding FPGA CAD suite for implementing user designs (the bitstreams) for the custom-defined eFPGAs.
[https://fabulous.readthedocs.io/en/]
This ecosystem integrates a range of open-source tools, including Yosys,...
Special-purpose hardware accelerators are critical for performance gains amid slowing technology scaling, but designers lack effective tools to build complex accelerators. Existing high-level synthesis (HLS) tools require intrusive source-level changes to attain high performance while most accelerator design languages excel only with simple kernels. In this talk, we present Allo [PLDI’24], a...
Cheby is an HDL tool which transforms a YAML description of a memory map into HDL code, C header, python constants or HTML documentation. The tool was designed to be flexible: it supports many buses, many kinds of peripherals (registers, memories, wires, submodules) as well as structural features like repetition. The tool was also designed to be extensible: it can easily be extended to add...
HDLRegression was developed to provide a reliable, efficient tool for regression testing of maintenance testbenches for UVVM and other FPGA project testbenches. It simplifies simulations with minimal changes—just a single comment in the testbench entity—making it easy to integrate into existing projects.
One big advantage is its independence from any specific verification framework,...
The diverse landscape of open-source HDL build systems, including VUnit, FuseSoC, HdlMake, HDLRegression and Bender, presents a challenge in terms of interoperability. While each tool offers unique advantages for managing HDL projects and their testbenches, their disparate methods for project description and dependency management impede the seamless integration of reusable libraries and IP...
nextpnr is an open source place and route toolchain for a range of FPGA devices. Through the himbächel and viaduct frameworks, it can easily be retargeted to new FPGAs, be it commercially available parts or eFPGAs for research purposes. This talk will cover some of the recent experiences in doing this, and some interesting insights into FPGA architecture variation and tradeoffs learnt in the process.
