31 August 2026 to 4 September 2026
Masarykova Kolej Congress Centre, Czech Technical University in Prague
Europe/Prague timezone

Modular and scalable DAQ system for GEM detectors

31 Aug 2026, 12:05
20m
Masarykova Kolej Congress Centre, Czech Technical University in Prague

Masarykova Kolej Congress Centre, Czech Technical University in Prague

Thákurova 550/1, 160 41 Prague 6
Oral presentation Electronics Plenary Session

Speaker

Bartłomiej Łach (AGH University of Krakow)

Description

This contribution presents the development of a new data acquisition (DAQ) system dedicated to the readout of Gas Electron Multiplier (GEM) detectors. The system is an evolution of a previously developed FPGA-based readout architecture [1], which has been successfully used in various applications with GEMs. Due to the obsolescence and unavailability of the FPGA device employed in the original design, a complete reorganization of the firmware, control infrastructure, and hardware migration was required.

The new system is built around the Enclustra MARS AX3 module, based on an AMD/Xilinx Artix-7 FPGA. To accommodate the new FPGA module, a dedicated base board was carefully designed. The board hosts the FPGA module, ADC circuitry, Ethernet interfaces and other supporting components. It is electrically and mechanically interfaced with a dedicated ASIC board, which connects directly to the GEM detector and performs the front-end signal processing using a dedicated readout ASIC.

A key novelty of the system is the completely redesigned firmware architecture, which was adopted and successfully adapted from our other project [2]. In particular, the system uses XFCP (eXtensible FPGA Control Platform), an open-source framework for FPGA control and communication that uses a source-routed packet-switched bus over AXI Stream and supports operation over UDP, together with a Python-based control framework. In the presented DAQ, XFCP serves as a main communication layer between the FPGA firmware and the host software. In parallel with the hardware redesign, the DAQ control system was also modernized by developing a new communication layer based on the Python language.
Another leap forward is system scalability, now it could readout as many channels -- therefore detectors as needed. The independent FPGA addressing and reliable time synchronization made it possible.

The contribution will discuss in detail the firmware architecture and XFCP integration, the readout hardware design, the data transmission path, and the upgraded DAQ control system. Preliminary measurement results illustrating the correct operation and functionality of the developed DAQ and detector readout will be presented as well.

The authors would like to acknowledge: M. Kopeć, S. Koperny, W. Dąbrowski

References

[1] B Mindur et al 2013 JINST 8 T01005
[2] B. Mindur et al 2025 JINST 20 P06040

Name of the speaker Bartłomiej Łach
Eligible for the Georges Charpak Young Scientist Award. yes

Authors

Bartosz Mindur (AGH University of Krakow (PL)) Bartłomiej Łach (AGH University of Krakow) Dr Piotr Kazimierz Wiacek (AGH University of Krakow (PL)) Mr Szymon Antkowiak (AGH University of Krakow) Tomasz Andrzej Fiutowski (AGH University of Krakow (PL))

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