Speaker
Raul Murillo Garcia
(University of California Irvine (US))
Description
The ATLAS Cathode Strip Chamber system consists of two end-caps with 16 chambers each. The CSC Readout Drivers (RODs) are purpose-built boards encapsulating 13 DSPs and around 40 FPGAs. The principal responsibility of each ROD is for the extraction of data from two chambers at a maximum trigger rate of 75 kHz. In addition, each ROD is in charge of the setup, control and monitoring of the on-detector electronics. This paper introduces the design and implementation of the CSC ROD firmware and software. The main features of this design include an event flow schema that decentralizes the different dataflow streams, which can thus operate asynchronously at its own natural rate; a ROD communication interface designed for high I/O throughput by minimizing the number of cycles necessary to move event data in and out of the DSPs; an event building mechanism that associates data transferred by the asynchronous streams but belongs to the same event; and a sparcification algorithm that discards uninteresting events and thus reduces the data occupancy volume, a crucial feature due to bandwidth limitations. The time constraints imposed by the high trigger rate have made paramount the use of optimization techniques such as the curiously recurrent template pattern and the programming of critical code in assembly language. The behaviour of the CSC RODs has been characterized in order to validate the performance of the software implementation.
Primary author
Raul Murillo Garcia
(University of California Irvine (US))
Co-authors
Andrew James Lankford
(University of California Irvine (US))
Andy Nelson
(University of California Irvine (US))
Mr
James Panetta
(SLAC)
Jianrong Deng
(University of California Irvine (US))
Mr
Leonid Sapozhnikov
(SLAC)
Mr
Michael Huffer
(SLAC)
Michael Schernau
(University of California Irvine (US))
Mr
Richard Claus
(SLAC)
Mr
Ryan Herbst
(SLAC)
