21-25 May 2012
New York City, NY, USA
US/Eastern timezone

Implementation of parallel processing in the basf2 framework for Belle II

24 May 2012, 13:30
4h 45m
Rosenthal Pavilion (10th floor) (Kimmel Center)

Rosenthal Pavilion (10th floor)

Kimmel Center

Poster Event Processing (track 2) Poster Session


Prof. Ryosuke ITOH (KEK)


Recent PC servers are equipped with multi-core CPUs and it is desired to utilize the full processing power of them for the data analysis in large scale HEP experiments. A software framework ``basf2'' is being developed for the use in the Belle II experiment, an upgraded B-factory experiment at KEK, and the parallel event processing is in its design. The framework accepts a set of plug-in functional modules and executes them in the specified order. The parallel processing is implemented so that the execution of the partial portion of the module chain can be parallelized, while keeping the other modules to be executed in a single path. This implementation expands the capability of the parallel processing from the trivial event-by-event to the pipeline processing of a module chain, keeping the single input and output stream. The execution of one path is performed in a UNIX process forked from the main program of basf2. The data passed between modules are a set of ROOT objects. In the parallel processing, whenever to pass the set to other process, they are streamed once and placed on a ring buffer implemented using UNIX IPC. The receiving process picks up the streamed packet from the ring buffer and restores the objects. The mechanism can be easily extended for the connection between PC servers over a network, which is used for the high level trigger application. The details of the parallel processing implementation in the basf2 framework will be discussed at the conference, which includes a report of the realistic performance of the processing in various cases.


The implementation of the parallel processing for the multi-core CPU in the Belle II software framework (basf2) is presented. It features the partial parallel execution of the module chain plugged in the framework, which enables the pipeline processing of modules in addition to the trivial event-by-event parallel processing.

Primary authors

Prof. Ryosuke ITOH (KEK) Soohyung Lee (Korea University)


Andreas Moll (MPI) Martin Heck (KIT) Prof. Nobuhiko Katayama (HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION) Sogo Mineo (University of Tokyo) Thomas Kuhr (KIT - Karlsruhe Institute of Technology (DE))

Presentation Materials