Speaker
Description
The TriglaV ASIC is a RISC-V-based SoC designed to address the requirements of future particle physics experiments. Fabricated in a TID-robust 28nm CMOS technology, it integrates fault-tolerance against single-event effects using TMR and ECC techniques. The architecture features a triplicated core, ECC-hardened memory blocks, hardened peripherals and interconnects. TriglaV was built via the SOCRATES (System-on-Chip Radiation-Tolerant Ecosystem) platform, enabling customization and reusable IP integration. This prototype aims to validate SOCRATES for developing resilient SoCs tailored to harsh conditions. Verification included formal methods, FPGA emulation and fault simulations. Dedicated on-chip circuitry for testability and fault observability facilitates upcoming testing and evaluation.
Summary (500 words)
The TriglaV chip represents a key step toward embedding radiation-tolerant System-on-Chips (SoC) into ASICs for High-Energy Physics (HEP) environments. Leveraging the open-source RISC-V architecture, TriglaV is the first prototype realized with SOCRATES (SoC Radiation-Tolerant Ecosystem), a platform targeting modular and reusable SoC design methodologies for harsh environments. SOCRATES addresses the rising complexity and cost of ASIC development in HEP by combining ASIC-grade radiation hardness with the software and design flexibility of microprocessors and SoC modularity.
The design of TriglaV is intended to validate SOCRATES and study how SoCs combined with
fault-tolerance strategies, can meet the stringent requirements of, e.g., on-detector electronics. A user-defined input architecture description lets SOCRATES’ tooling compose the full SoC by automatically inferring interconnection and introducing redundancy for fault tolerance. SOCRATES handles invoking of the compiler toolset and generation of hardware abstraction, enabling user-friendly software and firmware development.
For TriglaV, various countermeasures were applied against the high rate of single-event effects (SEE) expected to occur within the innermost radii of LHC Phase II detectors. The open-source Ibex RV32IMC processor was modified for full fine-grained triplication via TMRG to counter logic upsets. Memory Scrubbing and Protection Units (MSPU) were custom designed to control hamming-encoded memory accesses to two 32 kB dual-port SRAMs containing program instructions and data. The SRAM blocks include physical bit-interleaving to protect against multi-cell upsets throughout densely integrated SRAM cells. The MSPU units, themselves protected by triplication, control the configurable scrubbing of the memory content, preventing the accumulation of SEUs over time. Memories and processor are integrated through a triplicated interconnect. Peripherals, such as GPIO, timer and interrupt-control modules, are accessible through the hardened APB-RT peripheral interconnect. Versatile I/O capabilities including UART, JTAG and I2C allow multiple communication, booting and debugging options.
Various testability features were added to facilitate the detailed study of the design performance and footprint. Processor and memories were designed as individual IP blocks, allowing multiple power domains and power consumption measurements during testing. All triplicated and encoded logic was equipped with error correction counters, enabling module-level characterization of SEE rates during heavy-ion and laser testing. Triplicated and encoded error correction can be disabled for the processor and memories respectively, further allowing to assess the efficacy of the applied protection schemes in comparison with unprotected logic.
TriglaV was implemented in a commercial 28nm bulk CMOS technology, achieving an estimated operating frequency of 250 MHz and die size of approximately 1×2 mm². Verification was performed at various stages and levels of the design. They include post-synthesis formal verification of the core triplication, and fault injection testing applied to MSPU unit tests and to post-layout functional simulations at the system level.
In conclusion, TriglaV provides a compelling proof-of-concept toward the integration of programmable logic into future on-detector electronics for HEP experiments. With heavy-ion and laser test campaigns planned throughout 2025, the results from these studies are expected to contribute to the formulation of standards and best practices for resilient SoC design within the HEP community.
