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TWEPP 2025 Topical Workshop on Electronics for Particle Physics
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Europe/Athens
Rethymno, Crete, Greece
Rethymno, Crete, Greece
Aquila Rithimna Beach
Crete, Greece
Alex Kluge
(CERN)
Description
The workshop covers all aspects of electronic systems, components and instrumentation for particle and astro-particle physics such as: electronics for particle detection, triggering, data-acquisition systems, accelerator and beam instrumentation.
Operational experience in electronic systems and R&D in electronics for LHC, High Luminosity LHC, FAIR, neutrino facilities and other present or future accelerator projects are the major focus of the workshop.
Ojectives:
- Present original concepts and results of research and development for electronics relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities;
- Review the status of electronics for running experiments and accelerators;
- Identify and encourage common efforts for the development of electronics;
- Promote information exchange and collaboration in the relevant engineering and physics communities.
The main topics of the workshop will be recent research and developments in the following areas:
- Highly integrated detectors and electronics;
- Custom Analogue and Digital Circuits;
- Programmable Digital Logic Applications and Verification;
- Optoelectronic and Electric Data Transfer and Control;
- Packaging and Interconnect Technologies;
- Radiation and Magnetic Field Tolerant Systems;
- Testing and Reliability;
- Power Management and Conversion;
- Grounding and Shielding;
- Design Tools and Methods.
The workshop programme will include invited plenary talks, sessions for oral presentations, poster presentations.
Information about registration to the workshop and local organisation is available at: https://twepp25.org
Authors are invited to submit abstracts and summaries describing original developments and new contributions, including recent progress, in the workshop topic areas.
Abstracts (max. 100 words long) and summaries (max. 500 words long) along an optional file containing diagrams or plots must be submitted following this link: https://indico.cern.ch/event/1502285/abstracts/
The summary will be the basis for paper selection. The summary should describe quantitative specifications of the work, challenges, implementation and results relevant to the topics of TWEPP. Standard summaries targeted to physics or detector instrumentation conferences might need to be updated accordingly.
Submissions without comprehensive summaries will not be considered. Abstract submissions must be made by the presenters themselves.
Submissions by conference committees on behalf of speakers who will be nominated later are not accepted.
Each attendee may submit only one abstract and present only once, either an oral or poster presentation. The presenter’s physical presence at TWEPP is mandatory.
More information and guidelines about the abstract/summary submission can be found here: https://indico.cern.ch/event/1502285/abstracts/
The submission deadline is 30 April 2025 23:59 CET.
*** No extensions are foreseen ***
Abstracts will be made available at the time of the workshop and will include all contributions selected for either oral or poster presentation.
The proceedings of the workshop will be published in the peer-reviewed journal of Instrumentation, JINST.
Information concerning the workshop scientific programme and submissions is available at: https://indico.cern.ch/e/twepp2025
Enquiries can be directed to the Workshop Secretariat, by email at twepp@cern.ch
Local organisation information is be available on https://twepp25.org
Enquiries concerning the local organisation can be directed to the local organisation committee, by email at twepp2025@uniwa.gr
Scientific organisation
A. Kluge (CERN, CH, Chair)
J. Alme (UIB, NO)
S. Baron (CERN, CH)
C.F. Bedoya (CIEMAT, ES)
A. Boccardi (CERN, CH)
J. Cachet (CERN, CH, Secretary)
H. Chen (BNL, US)
S. Danzeca (CERN, CH)
M. French (RAL, UK)
D. Gascon (UB, ES)
M. Hansen (CERN, CH)
C.G. Hu (IPHC-IN2P3, FR)
I. Kopsalis, (NTUA, GR)
E. Kyriakis-Bitzaros (UNIWA, GR)
G. Lehmann Miotto (CERN, CH)
A. Rivetti (INFN, IT)
W. Snoeys (CERN, CH)
C. Soos (CERN, CH)
F. Vasey (CERN, CH)
E. Vilella (University of Liverpool, UK)
K. Wyllie (CERN, CH)
Organized by the University of West Attica and the National Technical University of Athens with the support from the European Organization for Nuclear Research (CERN)
Support
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Registration
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13:05
Opening MEGAS ALEXANDROS (Aquila)
MEGAS ALEXANDROS
Aquila
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10:00
Welcome by scientific committee 15mSpeaker: Alex Kluge (CERN)
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10:20
Welcome by local organisation committee 15mSpeakers: E. D. Kyriakis-Bitzaros, Niki Bai (NB Events- Conference Services)
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10:40
Scientific Activities in Institute of Plasma Physics & Laser (IPPL) of Hellenic Mediterranean University 15mSpeaker: Michael Tatarakis
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11:00
Νovel monochromatic and tunable gamma-ray light sources through exposure of acoustically modulated monocrystals to ultra-relativistic charged particles beams 20mSpeaker: Nektarios A. Papadogiannis
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11:25
Neuromorphic photonics for unconventional computing: towards ultra-fast and low consumption hardware acceleration, of machine learning models 45mSpeaker: Adonis Bogris
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12:15
Minoan Crete from Mythology to History 50mSpeaker: Gareth Owens
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Lunch break 1h 55m
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ASIC MEGAS ALEXANDROS Aquila
MEGAS ALEXANDROS Aquila
Conveners: Angelo Rivetti (Universita e INFN Torino (IT)), Angelo Rivetti (INFN - National Institute for Nuclear Physics), Marcus Julian French (Science and Technology Facilities Council STFC (GB))-
15:00
Performance and lessons learnt from System-Level testing of AltirocA, the Pre-Production ASIC for the ATLAS High Granularity Timing Detector 16m
The High Granularity Timing Detector (HGTD) for the ATLAS experiment, within the HL-LHC upgrade, uses Low Gain Avalanche Diode (LGAD) sensors for high-precision timing measurements.
AltirocA is the pre-production 225-channel readout ASIC, providing both luminosity and time-of-arrival measurements. The full system targets a resolution of 30 ps per hit initially and 70 ps after full irradiation.
Production of 25,000 AltirocA ASICs will begin this summer. Extensive testing was performed at various stages, including standalone, hybrid, and module setups. Tests were conducted under irradiation, in test-beams, and with a probe station at wafer level.
This contribution presents performance and difficulties encountered.Speaker: Nathalie Seguin-Moreau (OMEGA - Ecole Polytechnique - CNRS/IN2P3) -
15:20
The LiTE-DTU ASIC for the CMS ECAL upgrade: performance and experiences to treasure from first prototype to mass production, test and integration. 16m
The LiTE-DTU is an ASIC designed to digitize and transmit scintillation signals from the CMS Electromagnetic Calorimeter (ECAL) at HL-LHC. The chip was produced in TSMC 65 nm technology. The development process of the chip was not without hurdles, going through three prototype cycles and two engineering runs. Functionality and performance has been assessed in four test-beam campaigns. 96k chips have been packaged and tested in industry. We share our experience with the LiTE-DTU development, attempting to help saving time and effort in future similar efforts. Quantitative results from performance measurements and test statistics will complete this contribution.
Speaker: Stefano Argiro (Universita di Torino and INFN (IT)) -
15:40
Design to Production of HGCROC3 and H2GCROC3: Radiation-Hard Front-End ASICs for the CMS HGCAL 16m
The CMS High Granularity Calorimeter (HGCAL), developed for the HL-LHC, uses custom ASICs—HGCROC3 and H2GCROC3—to read out silicon sensors and SiPM-on-tile modules. These chips provide precise charge and timing measurements, digital processing for triggering, and are designed to operate in harsh radiation conditions. Version 3 of the chips implements all final features, with sub-versions A–E addressing bugs and improving radiation tolerance. Extensive testing has been performed in lab and beam environments. The presentation covers chip design, performance, SEE-related issues, and the automated production testing.
Speaker: Mr Damien Thienpont (OMEGA - Ecole Polytechnique - CNRS/IN2P3)
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Production AQUILLES (Aquila)
AQUILLES
Aquila
Conveners: Francois Vasey (CERN), Magnus Hansen (CERN)-
15:00
Factory Acceptance Test for the CMS Phase-2 back-end card Serenity-S1 16m
As part of the CMS phase-2 upgrade, the Serenity collaboration is developing Serenity-S1, a versatile FPGA-based processing card using the ATCA form factor. Widely adopted by various subdetector systems for the back-end data processing, a total of 777 boards are planned for production. This contribution presents the Factory Acceptance Test (FAT) designed for automated and efficient board commissioning directly at the factory, reducing test time to as little as 10 minutes. Initial results of the extended pilot production are shown including feedback from the assembler and subsequent improvements to the FAT.
Speaker: Hendrik Alexander Krause (KIT - Karlsruhe Institute of Technology (DE)) -
15:20
Large-scale tests for the characterisation of the lpGBT stuck at power-up issue 16m
The Low-power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. In 2023, almost 200,000 lpGBTs V1 were tested with a production test system that exercises the entire ASIC functionality to ensure its correct operation. Furthermore, qualification tests (Total Ionizing Dose, Single-Event Upsets…) were done for a dozen of lpGBTs. Despite the thorough production and qualification tests, a design issue named “stuck at power-up” was discovered, affecting a maximum of 0.9 % of delivered devices. The tools developed for the characterisation of this behaviour and the results obtained are given.
Speaker: Daniel Hernandez Montesinos (CERN) -
15:40
On-wafer 10 Gb/s signal testing of large-area monolithic active pixel sensors for the ALICE ITS3 and ePIC SVT detectors 16m
We present a novel 10 Gbps wafer-level testing system to characterize stitched Monolithic Active Pixel Sensors (MAPS) for ALICE ITS3 and ePIC SVT. Using a custom probe card and a 12-inch wafer-probe station, we demonstrate, for the first time in high-energy physics, 10 Gbps link characterization directly on wafer. Signal integrity was validated via bit error rate testing (BER < 10⁻¹²) and <70 ps jitter using an Enclustra Mercury FPGA. The setup, including FPC and VTRx+ optical readout, enables full-rate sensor evaluation prior to dicing. Probe card design and mechanical/electrical studies for reliable contact are also described.
Speaker: Stefano Caregari (Massachusetts Inst. of Technology (US))
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Coffee break 30m
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ASIC MEGAS ALEXANDROS Aquila
MEGAS ALEXANDROS Aquila
Conveners: David Gascon (University of Barcelona (ES)), Marcus Julian French (Science and Technology Facilities Council STFC (GB))-
16:30
Development of the CoRDIA detector: first performance estimations 16m
CoRDIA is an X-ray imager being developed, for Photon Science experiments at 4th generation Synchrotron Rings. Its goal is to be capable of continuous operation at 150k frame/s. Its Analog Front-End consists in a battery of adaptive-gain amplifiers and Analog-to-Digital converters, arranged in a pipelined, modular structure compatible with a compact pixel pitch (110um). A test structure has been designed using a 65nm process and was characterized, confirming expected performances in terms of noise, linearity, and adaptive gain operation at the operational speed. Some cross-talk issues have been identified, and an updated shielded layout was designed to solve them.
Speaker: alessandro marras (Deutsches Elektronen-Synchrotron) -
16:50
Challenges and strategies in verification of FastRICH ASIC for the LHCb RICH detector 16m
The FastRICH ASIC provides high-precision, triggerless readout for Upgrade-Ib of the LHCb RICH detectors. Demands of continuous data acquisition and varying hit rates across the detector impose unique challenges on the ASIC's design and verification. This work presents the verification strategy for FastRICH, focusing on functional correctness, timing performance, and operational robustness. The methodology includes simulations across occupancy scenarios, validation of timing precision, and stress testing under pile-up and high-rate conditions. Results demonstrate that FastRICH meets its performance requirements over the full range of expected occupancies. Key design and verification challenges are discussed, along with lessons learned for future developments.
Speaker: Matteo Lupi (CERN) -
17:10
Design and Evaluation of TriglaV: A Prototype SoC ASIC for Particle Physics Applications realized with the SOCRATES Platform 16m
The TriglaV ASIC is a RISC-V-based SoC designed to address the requirements of future particle physics experiments. Fabricated in a TID-robust 28nm CMOS technology, it integrates fault-tolerance against single-event effects using TMR and ECC techniques. The architecture features a triplicated core, ECC-hardened memory blocks, hardened peripherals and interconnects. TriglaV was built via the SOCRATES (System-on-Chip Radiation-Tolerant Ecosystem) platform, enabling customization and reusable IP integration. This prototype aims to validate SOCRATES for developing resilient SoCs tailored to harsh conditions. Verification included formal methods, FPGA emulation and fault simulations. Dedicated on-chip circuitry for testability and fault observability facilitates upcoming testing and evaluation.
Speaker: Anvesh Nookala (TU Wien)
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Production AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Francois Vasey (CERN), Magnus Hansen (CERN)-
16:30
A big step towards ATLAS ITk: Performance Characterization of the very first Loaded Local Support Structures 16m
In order to fulfill the demands of the High-Lumi LHC, the whole ATLAS experiment will undergo a major upgrade.
The current Inner Detector will be replaced by it‘s all-silicon successor - the Inner Tracker (ITk).
The smallest feature complete detector units of the ITk are so-called Loaded Local Supports (LLS).
These LLS have now been tested for the first time, in a complex test-setup, which includes all the features the future ITk will compromise - just in smaller scale.
This contribution will report on the results of the very first tests of this key element of the new ATLAS ITk.Speaker: Anna Swoboda (University of Innsbruck (AT)) -
16:50
Investigating the Operational Margin of ATLAS ITk Pixel Module Serial Powering 16m
ATLAS ITk Pixel detector modules are operated in serial power mode using a Shunt-LDO circuit inside the ITkPix readout chip. Due to cooling requirements, the system must be operated within stringent power constraints, resulting in only 10% of the current being burned in the shunt during nominal physics operation. Since the current consumption scales with hit activity and there are significant uncertainties on the measured values of the shunt currents, we investigate the module’s operational margins, and focus on establishing production quality control procedures that ensure the operability of modules within the given power-constrained system.
Speaker: Deion Elgin Fellers (Lawrence Berkeley National Lab. (US)) -
17:10
Reduction of constraints in the specification for the Hybrid circuit procurement for the CMS Phase-2 Upgrade 16m
Abstract
New sensor modules are currently being produced for the Tracker in the CMS Phase-2 Upgrade. These Strip-Strip and Pixel-Strip modules are the two main building blocks of the Outer Tracker. All together 8000 Strip-Strip and 5880 Pixel-Strip modules will be constructed and their construction requires the mass production of 47520 hybrid circuits. Despite careful preparation of the specifications for the hybrid circuit manufacturing, real production experience demonstrated the need to reduce and optimize some of the requirements. The presentation will focus on two example cases where the original requirements were analysed and reduced while still fulfilling the project requirements.Speaker: Mark Istvan Kovacs (CERN)
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Reception
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ASIC MEGAS ALEXANDROS Aquila
MEGAS ALEXANDROS Aquila
Conveners: David Gascon (University of Barcelona (ES)), Marcus Julian French (Science and Technology Facilities Council STFC (GB))-
09:00
Tracking performance of the 200 μm thick ARCADIA Fully Depleted MAPS 16m
The ARCADIA Main Demonstrator 3 (MD3), developed by the ARCADIA INFN collaboration, is a fully Depleted Monolithic Active Pixel Sensor in the LFoundry 110nm CIS technology. It features a custom backside process that allows for the full depletion of the high-resistivity substrate.
The first test beam on the MD3 was performed at the Fermilab Test Beam Facility in July 2024 with a 120 GeV proton beam, with a custom-made telescope constituted by two MD3 tracking planes and one MD3 Device Under Test.
This work presents the testbeam results, focusing on the tracking performance in terms of efficiency and spatial resolution.Speaker: Caterina Pantouvakis (Universita e INFN, Padova (IT)) -
09:20
Design and Characterization of the Monolithic ASIC for the Ultra-High-Resolution 100µPET Scanner 16m
This work presents the design challenges and characterization results of the novel 100µPET detector ASIC. The 100µPET project proposes an innovative scanner for small animals made of a stack of high-granularity, thin, full-reticle MAPS (30.2 x 22.8 mm²), and promises unprecedented volumetric resolution of 0.022 mm³. The chip features ~25k hexagonal pixels with 93 µm side in 130 nm SiGe BiCMOS. The in-pixel frontend achieves an ENC < 200 electrons, with 200-ps-level jitter and power consumption below 100 $\text{mW/cm}^2$. The ASIC includes 150 ps resolution TDCs, a pipelined 50 MHz projection-based readout, and handshaking protocol for daisy-chained, single line readout.
Speaker: Carlo Alberto Fenoglio -
09:40
Yield and performance validation of the MOSS, the first stitched MAPS prototype for ALICE ITS3 16m
The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in a high-energy physics detector. The first stitched prototype, the Monolithic Stitched Sensor (MOSS), underwent testing that confirmed yield compliance with ITS3 requirements. Linearity between time-over-threshold and deposited energy was validated from 1.8 to 5.9 keV using $^{55}$Fe X-rays. In-beam tests confirmed the device meets ITS3 efficiency (99%), and fake-hit rate targets (< 10$^{-6}$ hits pix$^{-1}$ events$^{-1}$), with performance sustained up to expected irradiation levels (400 krad, 4$\cdot$10$^{12}$ 1 MeV n$_{eq}$). This talk presents validation steps and characterisation results.
Speaker: Marius Wilm Menzel (Heidelberg University (DE))
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Systems AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Csaba Soos (CERN), Ken Wyllie (CERN)-
09:00
Results of the CMS Phase-2 TEPX system tests 16m
The Compact Muon Solenoid (CMS) detector will undergo a major upgrade (Phase-2) to take advantage of the increased luminosity provided by the High-Luminosity LHC (HL-LHC). As part of this upgrade, the Tracker Endcap Pixel detector (TEPX) will be introduced as a subsystem of the Phase-2 Inner Tracker, extending the pseudorapidity coverage up to |η|<4. The TEPX consists of eight double-layer disks, split into two halves, and will incorporate a total of 1408 quad-chip hybrid pixel modules. This work presents system tests conducted on TEPX layer prototypes, including electrical and thermal characterization, as well as evaluation of data transmission performance.
Speaker: Valeriia Lukashenko (University of Zurich (CH)) -
09:20
Performance of the ALICE Zero Degree Calorimeters readout system in ion-ion collisions at the LHC. 16m
The Zero Degree Calorimeters (ZDC) of the ALICE experiment at the LHC were designed to characterize the event and monitor the luminosity in heavy-ion measurement. The ZDC readout system developed for Run 3, based on a commercial 1 GSps 12 bit digitizer assembled on an FPGA Mezzanine Card, is able to operate in self-triggered mode allowing the acquisition of all collisions without dead time. The architecture of the readout system and the ZDC performance during ion-ion collisions are presented, particularly the 2024 Pb–Pb results, where the readout rate for the channels of the most exposed calorimeters was ≈ 1.4 Mevents/s.
Speaker: Stefan Cristi Zugravel (INFN Torino (IT), DET Politecnico di Torino (IT)) -
09:40
Readout Electronics for the Photon Detection System of the DUNE Far Detectors 16m
The Photon Detection Systems of the DUNE Far Detectors (FD-HV and FD-VD) use large SiPM arrays read out by low-noise, discrete-component amplifiers operating in liquid argon. Signals are transmitted to warm electronics either electrically (in FD-HD and in FD-VD membrane modules) or optically (in FD-VD cathode modules). The warm readout board, DAPHNE, interfaces with all these cold electronics variants, performing signal digitization, online triggering, filtering and data transfer, using an FPGA SoM. This contribution presents the design, implementation, and test results of the complete readout chain, highlighting challenges and solutions for achieving low-noise, high-performance signal acquisition in a cryogenic environment.
Speaker: Paolo Carniti (Universita & INFN, Milano-Bicocca (IT))
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Coffee break 30m
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Invited
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10:30
From detector design to physics insights: how instrumentation shapes particle physics measurements 45m
In recent decades, instrumentation for high-energy particle and nuclear physics has advanced dramatically, enabling the detection of rare signals with unprecedented precision and leading to numerous discoveries and high-accuracy measurements. To meet the stringent requirements of modern physics experiments, particle detectors must achieve exceptional spatial, momentum, and time resolution—continuously pushing the frontiers of current technology.
This presentation offers a concise overview of the process of converting raw data from a particle detector into meaningful physical information about particles produced in hadronic collisions. It focuses on track and decay-vertex reconstruction, and examines how varying detector specifications influence physics performance. These principles are illustrated through a real-world example: the upgraded Inner Tracking System (ITS3) of the ALICE experiment at the CERN Large Hadron Collider. ITS3 employs an innovative technology that, for the first time, enables the use of ultra-thin, wafer-scale, bent silicon sensors—minimizing the detector's material budget to an unprecedented level.
BIOGRAPHY
Fabrizio Grosa received his degree in Nuclear and Subnuclear Physics from the Università di Torino and earned a PhD in Physics from the Politecnico di Torino (Italy) in 2020. After completing a postdoctoral research position at INFN, he joined CERN in 2021, where he is currently a research staff member.He has been a member of the ALICE Collaboration at the CERN Large Hadron Collider since 2015. His research focuses on the measurement of particles containing heavy quarks (charm and beauty) produced in high-energy proton-proton and heavy-ion collisions. These studies aim to test quantum chromodynamics (QCD) — the theory describing the strong nuclear force — under extreme conditions of temperature and energy density.
Within the ALICE Collaboration, he has held several leadership roles, including coordination of the physics working group dedicated to the study of hadrons containing heavy quarks and oversight of the work package focused on simulation and performance studies for the upcoming upgrade of ALICE’s silicon vertex detector, the Inner Tracking System 3. Most recently, he has been appointed deputy trigger coordinator of the ALICE experiment.
Speaker: Fabrizio Grosa (CERN)
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ASIC MEGAS ALEXANDROS Aquila
MEGAS ALEXANDROS Aquila
Conveners: David Gascon (University of Barcelona (ES)), Marcus Julian French (Science and Technology Facilities Council STFC (GB))-
11:20
ALICE ITS3 MOnolithic Stitched sensor with Timing (MOST): design overview and measurements highlights 16m
The MOST (Monolithic Stitched Sensor with Timing) is a 25.9\,cm-long wafer-scale pixel sensor prototype that bridges generic R\&D for future High Energy Physics (HEP) detectors with the developments aimed for the ALICE Inner Tracking System (ITS3).
Its main purpose is to investigate the yield of high-density pixel architectures, assess the timing capabilities of asynchronous readout, investigate an alternative sensor biasing scheme, evaluate yield enhancing power segmentation and verify a robust bias distribution method resilient to fluctuations of supply voltages.This contribution presents both the design overview of the MOST chip and key measurements that validate its functionality and performance.
Speaker: Szymon Bugiel (CERN) -
11:40
Development of CMOS LGAD sensors for the ALICE 3 Time of Flight detector 16m
The ALICE 3 Time of Flight detector requires a time resolution below 20 ps to allow for electron and charged hadron identification from 15 MeV/$c$ (forward e/$\pi$ separation) to 4 GeV/$c$ (p/K separation).
The expected event rate, of about 280 kHz/cm$^2$, makes monolithic CMOS sensors very attractive.
However, their time resolution is still far from the experiment needs.
A solution is to incorporate a moderate gain (10-30) in the active region. For this, a dedicated R&D in a standard 110nm node is underway.
In this presentation, the device concept is discussed, and the experimental results obtained so far are presented.Speaker: Mr Umberto Follo (Politecnico e INFN Torino (IT)) -
12:00
3D-integrated sensors for particle physics detectors 16m
The goal of our project is to develop technology that enables large-scale particle detectors with 3D-integrated ASIC designs to achieve 10 μm position and 10 ps precision timing resolutions. The sensors used in this application are based on Low-gain avalanche diodes (LGADs), developed in a standard foundry CMOS process. We also developed a readout ASICs to match these sensors in the TSMC 28 nm CMOS process. Target performance is < 20 ps timing resolution, while maintaining the power consumption below 1 W/cm2. We will present the details of the designs and the results of the first measurements.
Speaker: Davide Braga (FERMILAB)
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Systems AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Csaba Soos (CERN), Sophie Baron (CERN)-
11:20
Readout electronics for the LHCb upgrade 2 muon system 16m
The contribution is focused on the new readout electronics for the µ-RWELL-based detectors that should be installed at the LHCb upgrade2 muon system. It is based on the FATIC (FAst Tuning Integrated Circuit) ASIC, providing charge and timing measurements of acquired signals. A first version of the chip, readout and controlled by a custom FPGA board, has been tested both in laboratory and during a beam test with µ-RWELL-prototypes and results are discussed. A new FATIC version with dead time reduced by a factor 10 is being designed thus improving the chip performance at the LHCb upgrade2 expected signal rates.
Speaker: Liliana Congedo (Universita e INFN, Bari (IT)) -
11:40
Integration of the Upgraded CMS Data Readout System for LHC Phase-2 16m
The CMS Phase-2 upgrade of the CMS Data Acquisition (DAQ) system is based on the DAQ and Timing Hub (DTH) custom board. The DTH serves as an interface, connecting sub-detector front-end electronics to the DAQ, as well as timing and trigger control and distribution system. This work focuses on the DAQ functionality of the DTH, detailing the current status of the project, including the DAQ firmware and control software. First integration with Phase-2 sub-detectors and future plans are presented.
Speaker: Polyneikis Tzanis (CERN) -
12:00
Unified Data Acquisition System for the CMS MIP Timing Detector for High Luminosity LHC 10m
The CMS MIP Timing Detector (MTD) will deliver a timing resolution of ~30 ps at the beginning of High Luminosity LHC. A unified MTD data acquisition (DAQ) system has been developed to provide data readout, as well as comprehensive control and monitoring functionalities. Precision timing distribution is critical for ensuring stable synchronization and robust calibration procedures. The unified DAQ system spans both barrel and endcap, managing a large number of high-speed optical links, supporting millions of readout channels. The system is powered by Serenity ATCA boards with AMD/Xilinx VU13 FPGAs and built on custom, modular firmware and software frameworks.
Speaker: Mehmet Ozgur Sahin (Université Paris-Saclay (FR))
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Lunch break 1h 20m
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Poster 1 Athina hall
Athina hall
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Radiation Qualification of Cryogenic Instrumentation Electronics for CERN’s HL-LHC Upgrade and LHC Infrastructure 20m
At CERN, for the High-Luminosity upgrade of the Large Hadron Collider (LHC), the cryogenics instrumentation team will produce 2,000 electronic cards to support 1,800 new instrumentation channels. These cards will integrate with the LHC’s existing infrastructure of 10,000 transducer cards and are therefore designed to be radiation tolerant. This paper describes the results of two irradiation test campaigns conducted at CERN’s CHARM facility in 2023 and 2024, aimed at validating the performance and resilience of the new electronics in a representative radiation environment.
Speaker: Nikolaos Trikoupis (CERN) -
14:20
Filters and redundancies: an exploration of novel coherent noise filters for high energy physics 20m
This work presents radiation-tolerant implementations for the SALSA front-end readout ASIC through redundancy methods applied to two median-finding algorithms designed for coherent noise suppression. Bit-wise Median Finder (BWMF) and Combinatorial Sum Median Finder (CSMF) were implemented in TSMC 65nm and IHP 130nm technologies and evaluated in terms of area, power, latency, and flip-flop count. Three redundancy techniques were appliedin this work to compare their impact on area and power: simple TMR, full TMR, and temporal TMR (TTMR). The simple and full TMR approach was applied in both algorithms to establish comparisons and TTMR was applied to CSMF as an improvement.
Speaker: Felipe William da Costa (Polytechnic School of University of São Paulo) -
14:40
Development of Low-Mass Flex PCB and Nanowire Interconnect Technologies for HEP Module Integration 20m
The development of lightweight flex PCBs and nanowire-based thermal interfaces for low-mass, high-performance detector modules are presented. A novel manufacturing approach enables flex circuits with double-sided pad access, assembled using ACF and gold studs. Signal integrity was simulated and validation trials conducted on test structures. For thermal management, sintered and glued nanowire interfaces were evaluated against silver paste and adhesives. These results provide quantitative design guidance for minimal-mass, scalable packaging in HEP detectors.
Speaker: Abhishek Sharma (CERN) -
15:00
A 11-Gbps CMOS-logic serializer core for high-energy physics experiments 20m
High-speed serial transmitters are commonly used in various fields, including high energy physics experiments, where the data volume has significantly increased due to detector upgrades. We present a CMOS-logic serializer core designed for front-end detector data transmission in a 55 nm technology. The prototype design features a 32-to-1 binary-tree multiplexer, an LC-based phase-locked loop, and a current-mode logic driver. The total jitter at 10.24 and 11.09 Gbps is approximately 24.5 ps and 30 ps, respectively, with power consumption of 96.2 mW and 97.4 mW. The internal timing margin accommodates a power supply variation from 1.15 V to 1.4 V.
Speaker: Xiaoting Li (IHEP) -
15:00
A 65nm CMOS Four-Channel Readout ASIC for ATLAS Muon Drift Tubes: 5-100fC detection, 15ns Peaking time, and 8mV/fC Sensitivity 20m
This paper presents performance of readout electronics for the ATLAS muon-chamber (MDT) to detect and measure the charge resulting from proton-proton collisions. The design emphasizes speed, robustness, and efficiency in area and power. It achieves a peaking time of 15 ns with 60-pF detector capacitance and 4 ns without it. The circuit demonstrates linear sensitivity of 1 mV/fC at the charge-sensitive preamplifier (CSP) output and 8 mV/fC at the shaper output. Charge information in the range of 5–100 fC is extracted via time-over-threshold (ToT) decoding. Implemented in 65 nm CMOS technology, the design operates at a 1.2 V supply voltage.
Speaker: Syed Adeel Ali Shah (University of Milano Bicocca) -
15:00
A Low-Power Timing Chip Prototype for Strip LGAD Readout 20m
This report presents a single-channel readout chip LATRIC0 designed for the CEPC Out Tracker detector. The chip integrates an event-driven ring oscillator time-to-digital converter in a 55 nm process, achieving an average bin-size of 28.9 ps for both time over threshold and time of arrival. The average power consumption for measurement is below 1 mW. To mitigate the inconsistencies between each bin sizes, quantization cells are carefully customized. Both the simulated integral and differential non-linearity are below 0.25 LSB. The power consumption of the pre-amplifier and TDC block is less than 7 mW.
Speaker: Jingbo Ye (Chinese Academy of Sciences (CN)) -
15:00
A radiation tolerant digital quench detector for the LHC's superconducting main dipole magnets 20m
During LHC Long Shutdown #3, the base layer quench detectors for the LHC main dipoles will be upgraded to a new type. The new FPGA-based quench detectors are equipped with two galvanically isolated, high-resolution input stages that digitise the two dipole aperture coil voltages. This new digital design allows the quench detection settings to be changed remotely. As the detectors are installed below the dipole magnets, they have to withstand the radiation present during LHC operation, which can exceed 100 Gy/y at certain locations. This paper discusses the design, testing, component selection and implementation of the new detector boards.
Speaker: Jens Steckert (CERN) -
15:00
A Shunt-LDO for the Electron Ion Collider in a 110nm CMOS Process 20m
In this work we report on the development of a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and can supply up to 1A at a voltage of 1.1 to 1.4V. Simulated PSRR at DC is -56dB. Safety features such as load overcurrent protection and the ability to shunt the current of failed parallel SLDOs are included. A first prototype has been submitted. In this work we will report simulation results and early test results.
Speaker: Iain Sedgwick (Science and Technology Facilities Council STFC (GB)) -
15:00
Advancements in Power Supply Systems for the High-Luminosity Large Hadron Collider (HL-LHC) 20m
This paper examines the latest advancements in power supply technologies for the HL-LHC, particularly focusing on the EASY6000 power supply system. Highlighted for its enhanced radiation tolerance, the system supports safe and efficient operations over the HL-LHC's extended lifespan. The study evaluates the system's performance in challenging environments, essential for optimizing power delivery to new detectors' front-end. The research, conducted over five years by CAEN, involved extensive testing of components likewise complete boards in varied radiation fields and magnetic orientations. It showcases innovative techniques and progresses ensuring efficient power delivery for future high-energy physics experiments.
Speakers: Andrea Guatteri, Dr Ferdinando Giordano -
15:00
Analysis of Frequency Tuning Techniques for SET Resilience in Ring Oscillators using a Calibrated SEE Model 20m
This work evaluates how stage count, gate length, and load capacitance tuning affect radiation tolerance in CMOS inverter based ring oscillators using a newly developed Dynamic Voltage-Dependent (DVD) Single-Event Transient (SET) model validated in a 65\,nm CMOS technology. The model captures n- and p-type Single Event Phase Transients (SEPTs). Simulations are performed under worst-case conditions (1.15,V supply, 75$^\circ$C, slow-slow corner) to evaluate maximum timing effects. While stage count tuning preserves SEPT sensitivity, length and capacitance scaling degrade timing error robustness. This study offers guidance on selecting frequency control techniques that minimize radiation-induced timing errors in ring oscillators.
Speaker: Venkata Sathyajith Kampati (KU Leuven (BE)) -
15:00
CALOROC1B: an integrated front-end ASIC to readout SiPMs for the ePIC detector at EIC 20m
The CALOROC1B ASIC has been designed to read out the SiPMs for the ePIC detector at the EIC collider. Each of its 36 channels is composed of a high-gain preamplifier, two low-power preamplifiers, a dynamic gain switching mechanism, a shaper, and two ADCs to read the energy, with a discriminator connected to a TDC for time-of-arrival measurements. This work presents the ASIC architecture and its simulation results. The ASIC has been designed to read large SiPMs (up to 10nF), be resilient to radiation, and have a large dynamic range (up to 140k measured as Qmax/Noise) while keeping a good resolution.
Speaker: Pedro Pablo DUMAS ZIEHLMANN (CNRS) -
15:00
Characterisation of Pixel Detectors with Test Beams for the Inner Tracker Upgrade of the ATLAS 20m
The High Luminosity LHC upgrade demands enhanced tracking, prompting a full replacement of ATLAS’s Inner Detector with the all-silicon Inner Tracker (ITk). Spanning 33–291 mm from the beam pipe, ITk will use hybrid pixel detectors with 65 nm CMOS chips. The inner region, facing extreme radiation, will feature 3D pixel sensors, while the outer regions use planar sensors. Testing in 2024–2025 evaluated two chip versions (v1 and v2) under high fluence. This talk presents tracking performance pre/post-irradiation, front-end electronics operability, and TOT-to-charge calibration, supported by results on IV characteristics, hit efficiency, and noise behaviour across operational settings.
Speakers: Mahima Sachdeva (The Barcelona Institute of Science and Technology (BIST) (ES)), Simone Ravera (INFN e Universita Genova (IT)) -
15:00
Characterization of an asynchronous front-end circuit in 28 nm CMOS for pixel readout in future HEP experiments 20m
This work presents the design, implementation, and characterization of a 28 nm CMOS readout channel for pixel sensors in future HEP experiments. The channel adopts the Time-Over-Threshold technique for the digital conversion of the detector signal amplitude and integrates a low-noise, charge-sensitive amplifier based on a composite cascode gain stage. A prototype chip, featuring an 8x32 array of readout channels, was submitted in Q3-2024 and is currently available for characterization. The paper will discuss the design and the experimental validation of the front-end, focusing on the main analog performance parameters of the channels integrated in the prototype chip.
Speaker: Luigi Gaioni (University of Bergamo and INFN (IT)) -
15:00
Characterization of the bPOL48V GaN DC-DC Buck Converter for R&D on Future Particle Collider Power Systems 20m
The bPOL48V is a DC-DC Point-Of-Load (POL) buck converter developed at CERN and characterized at RWTH Aachen University under the DRD7 program. The bPOL48V is designed to address power distribution challenges of next-generation high-energy physics experiments by enabling power delivery at higher voltages and lower currents in supply cables, thereby minimizing power losses. It supports a higher input voltage (48V) compared to existing solutions by using a CERN-designed GaN controller with a commercial GaN power stage. The bPOL48V has been characterized in various setups, and its performance results will be presented, covering efficiency, stability, and both emitted and conducted noise.
Speaker: Joelle Savelberg (Rheinisch Westfaelische Tech. Hoch. (DE)) -
15:00
Charge collection parameterization of MALTA2, a Depleted Monolithic Active Pixel Sensor 20m
In this work, MALTA2 sensors were tested at the CERN SPS Test Beam using the MALTA beam telescope, as well as with a pulsed laser employing the Edge Transient Current Technique (Edge-TCT). Sensors irradiated up to a fluence of $5 \times 10^{15}~1~\mathrm{MeV}~n_{\mathrm{eq}}/\mathrm{cm}^2$ were characterized in terms of tracking efficiency and cluster size, using the grazing angle technique. The active depth of the MALTA2 sensor was estimated through both grazing angle and Edge-TCT methods. Finally, progress on the next generation of MALTA sensors will be discussed.
Speaker: Lucian Fasselt (DESY) -
15:00
Design and first results of COFFEE3, a pixel sensor prototype using 55nm HVCMOS process 20m
Motivated by the Upstream Pixel tracker in the LHCb Upgrade II and future electron-positron collider, COFFEE series chips are developed in a 55nm HVCMOS process. While maintaining a fine spatial resolution and reasonable power consumption, we aim to achieve a few nanosecond timing under hit density up to 100 MHz/cm$^2$. Building on the first validation chip with in-pixel amplification, a new prototype, COFFEE3, is designed and being tested. Two schemes for high density readout were included: analog pixel with improved column readout and a digital pixel with TDC. This talk will discuss the design details and shows the first results.
Speaker: Xiaomin Wei (Northwestern Polytechnical University (CN)) -
15:00
Design of a 25 Gb/s High-Voltage Radiation-Tolerant Driver for SiPh Modulators in 28 nm CMOS Technology 20m
This work presents the design of a radiation-tolerant driver for high-speed electro-optical transmitters. The driver delivers 25 Gb/s modulation signals with a 3.6 V swing, bridging the voltage gap between 28 nm CMOS technology (rated for 0.9 V) and silicon-photonics devices. A multi-voltage domain approach allows operation from a single supply, optimizing power efficiency and minimizing area. This driver enables achieving the 100 Gb/s downlink target on a single fiber, realized by combining four 25 Gb/s drivers in parallel, using wavelength division multiplexing, for high-speed communication systems in future experiments.
Speaker: Gabriele Ciarpi (CERN) -
15:00
Design of a Radiation-Tolerant Thermal Control Unit for Silicon Photonics Modulators in 28-nm CMOS Technology 20m
High-energy physics experiments require radiation-tolerant optical links for high-speed data communication. Ring modulators offer high bandwidth but are sensitive to temperature and process variations, necessitating thermal control to stabilize their resonant wavelengths. This work presents a radiation-tolerant thermal control unit designed for micro-ring modulators. The system integrates a first-order delta-sigma ADC to monitor photodiode current, a digital controller, and a high-resolution delta-sigma DAC driving a micro-heater. Simulations demonstrate that the ADC achieves over 60 dB SNR, while the DAC enables temperature control with 0.38 $^\circ$C resolution. These results establish a foundation for reliable thermal management in high-speed, radiation-tolerant optical links.
Speakers: Gabriele Atzeni, Gabriele Ciarpi (CERN) -
15:00
Design, simulation and characterization of the ALICE ITS3 MOSS analog front-end 20m
The upgrade of the ALICE vertex detector (ITS3) with wafer-scale stitched MAPS targets an orthogonal MIP detection efficiency >99%, with a fake-hit rate <0.1pixel⁻¹s⁻¹ and a power budget of 40mW/cm². The MOSS wafer-scale monolithic sensor analog front-end, featuring ~0.55mV/e- gain and ~16e- rms of noise and threshold dispersion, was designed, prototyped and measured confirming these performance targets. Measurement results suggest that the digital readout signal (STROBE) injects noise into the pixel matrix, indicating an even better effective front-end. In this work, front-end design, simulation and measurement results will be presented together with a discussion on the observed STROBE-related effect.
Speaker: Simone Emiliani (CERN) -
15:00
Development of a triggerless readout energy measuring and timestamp ASIC for silicon microstrips sensors 20m
The new version of ToASt as a radiation tolerant readout for silicon microstrips sensors, has been produced and it is now under characterization. It is implemented in a 110 nm commercial CMOS technology, and it is synchronous to a 160 MHz clock. A common time stamp is used to provide both particle time of arrival and energy particle information with ToT technique. Triple logic is applied to all configuration registers of 64 channels and in the global logic circuit for protection against single event upsets. Enclosed gate layout has been used for the analog switches to protect against TID leakage.
Speaker: Daniela Calvo (INFN Torino (IT)) -
15:00
ETROC2 as the final version for CMS MTD Endcap Timing Layer (ETL) upgrade 20m
Abstract (100 words)
The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL. The ETROC2 chips have been extensively tested, and the results have been presented at last TWEPP. We will present here new results including the bump bonding yield improvement study, the time walk correction (WTC) generality study with one pixel WTC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors and irradiated sensors, and readiness for the ETROC2 production for CMS ETL upgrade.
Speaker: Tiehui Ted Liu (Fermi National Accelerator Lab. (US)) -
15:00
Evaluation of Total Ionising Dose effects on HV-CMOS pixel sensors in 150 nm technology 20m
This work presents the Total Ionising Dose (TID) radiation assessment of HV-CMOS pixel sensors fabricated in the LFoundry 150 nm process. Two prototypes, UKRI-MPW1 and RD50-MPW4, were irradiated with X-rays up to 100 Mrad while biased and operated under designed conditions. Post-irradiation measurements on UKRI-MPW1 revealed increased leakage current, reduced breakdown voltage, and parasitic inter-pixel resistive channels due to Si-SiO$\mathrm{_2}$ interface charge accumulation. RD50-MPW4 was operated throughout irradiation to monitor real-time power consumption and evaluate pixel performance at different dose intervals. These results complement existing Non-Ionising Energy Loss (NIEL) radiation studies, supporting the deployment of HV-CMOS sensors in high-radiation environments.
Speaker: Chenfan Zhang (University of Liverpool (GB)) -
15:00
first tests of laser power transmission for HEP 20m
We present the initial findings of a silicon photomultiplier powered by a laser and exposed to a light source. The study will explore various parameters of both the laser and the photomultiplier.
Speaker: Yan Benhammou (Tel Aviv University (IL)) -
15:00
High-speed readout controller and communication protocol for pixel detectors 20m
This paper presents the design of high-speed readout controller dedicated for pixel detectors. Communication with imaging sensors is asymmetric in its nature. Configuration, calibration and control data transfers are typically not time-critical or are composed of relatively short commands. In the other direction, it is desired to transfer image data as fast as possible. Having that in mind, the developed controller is divided into control path and readout path. Control path is responsible for loading configuration data and controlling chip operation. Readout path on the other hand is unidirectional and designed for high data throughput by utilizing multigigabit serializer.
Speaker: Dr Piotr Otfinowski -
15:00
Limits of Successive Approximation Register (SAR) ADC architecture 20m
This work presents a 12-bit ADC implemented in 65 nm CMOS technology, designed for on-chip conversion in high-energy physics experiments, It is also intended for use as an IP block within the DRD7 collaboration framework. The architecture features a fully differential Capacitive DAC, a double-tail latched comparator and an asynchronous digital controller. Post-layout simulations demonstrate an ENOB of 11.6 bits at 50 MSps with a power consumption kept below 850 µW at this rate. This work aims at exploring the performance boundaries of SAR architectures in 65 nm technology. Full characterization of the ADC will be conducted later this year.
Speaker: Miquel Ribalda Galvez (University of Barcelona (ES)) -
15:00
Measurement of the SEU rate and the demonstration of automated recovery for the Kintex-7 FPGA on TGC readout boards in the ATLAS Experiment at HL-LHC 20m
Results are presented for the measurement of Single Event Upset (SEU) rate and recovery demonstration for the Kintex-7 FPGA on Thin Gap Chamber (TGC) readout boards for the ATLAS experiment at HL-LHC. The readout boards were installed on the TGC detectors in the ATLAS detector area. We observed 133 single-bit and 5 multi-bit SEU errors in the configuration memory of the Kintex-7 FPGA during Run-3 data taking of pp collisions at 13.6 TeV with an integrated luminosity of ~90 /fb. All the errors were automatically recovered by the soft error mitigation controller implemented in the Kintex-7 FPGA.
Speakers: Daisuke Hashimoto (Nagoya University (JP)), Yasuyuki Horii (Nagoya University (JP)) -
15:00
MightyPix – A Novel High Voltage Monolithic Active Pixel Sensor for the proposed LHCb Mighty-Tracker 20m
MightyPix is a novel high-voltage monolithic active pixel sensor developed for the proposed LHCb Mighty-Tracker. It is designed to handle hit rates up to 40 MHz/cm² with 3 ns timing precision and a high radiation tolerance with NIEL and TID of up to 3×10^14 neq/cm² and 40 MRad. Building on prior prototypes MightyPix1 and LF-MightyPix, MightyPix2 integrates a segmented matrix architecture with enhanced readout and control systems, including TFC and ECS interfaces, a synthesized DDR serializer and an improved column-drain architecture with hit preloading. Designed in AMS’ aH18 process, MightyPix2 achieves 99.5% readout efficiency in simulations and supports serial powering.
Speaker: Nicolas Striebig (KIT - Karlsruhe Institute of Technology (DE)) -
15:00
On-Chip Packets Sorting for High-Throughput Data-Driven Pixel Detectors in a 28 nm CMOS Technology 20m
Data-driven readout architectures produce unsorted streams of data packets with variable latency. Reconstructing an event frame, defined as grouping packets from the same time window, requires a sorting operation. Its complexity increases proportionally to the occupancy and distance between the packets’ source and the sorting step.
This contribution presents an on-chip bucket sorting module for high-throughput applications processing up to 200 Gbps with <1% packet loss. Implemented for the LA-Picopix ASIC using 28nm technology and dual-port SRAMs, the module achieves a power consumption <250 mW and an area footprint <7 mm², operating at 320 MHz with fully triplicated control logic.Speaker: Francesco Enrico Brambilla (KU Leuven (BE)) -
15:00
Performance and automatic calibration scheme of the waveform sampler in the ETROC2 ASIC chip 20m
The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge injection test data. After calibration, the baseline random error is reduced by a factor of 2.5–3 compared to the default calibration, and a 5% charge measurement precision is achieved in 15 fC charge injection tests.
Speaker: Dr Jinyuan Wu (Fermi National Accelerator Lab. (US)) -
15:00
Performance of a New Generation Controller for the Power Systems of HEP experiments 20m
The performance of the new CAEN controller R6060 was measured on a real slice of the ATLAS RPC detector, using 15 Easy3000 modules of various types, and compared with the present controller A1676A. An average improvement of a factor 30 was found for the response time of the single command execution, and of about 5 for the parameter refresh. Considering the test setup, an additional factor of at least 4 to apply to the above-mentioned factors is expected in real experimental conditions.
Speaker: Emanuele Romano (Pavia University and INFN (IT)) -
15:00
PRISME: A radiation tolerant low power Phase-Locked Loop in a 65 nm technology for precision clocking at EIC 20m
The PRISME chip is developed as a new radiation tolerant PLL for clock generation with a jitter lower than ten ps. This block is designed in the TSMC 65 nm technology, to allow its integration in future readout ASICs that are considered for the EIC project. The PLL block is a basis of a low-power standalone clock fan-out ASIC with phase adjustment capabilities. A first prototype was design and tests showed that the nominal PLL frequency was reached with a wide input frequency range. The PRISMEv1 will come back from foundry in May 2025 implementing the improved noise performance PLL.
Speaker: Mr Florent Bouyjou (CEA IRFU - Université Paris-Saclay (FR)) -
15:00
Probe station tests of AltirocA wafers for ATLAS HGTD 20m
The High Granularity Timing Detector (HGTD) is a Phase II upgrade project for ATLAS, aimed at providing precise time measurements for tracks to reduce the impact of pile-up effects.
The read-out is performed by ALTIROCA which is a 2x2 cm² CMOS 130nm ASIC with 225 channels.
In order to build the detector, about 27000 ASIC will be produced and tested at the wafer level using a probestation. The poster will describe the acquisition system as well as the results obtained for the pre-production.Speaker: Jimmy Jeglot (Université Paris-Saclay (FR)) -
15:00
Radiation hardness compatibility of vacuum gauge electronics for the HL-LHC era 20m
The HL-LHC upgrade will lead to increased radiation levels in the LHC tunnel. Consequently, hundreds of vacuum gauge conditioning electronics deployed throughout the LHC must be replaced by new radiation tolerant designs. The development of radiation tolerant electronics followed the CERN radiation hardness assurance protocol. Component and system-level radiation tests have been performed at different radiation facilities. Issues encountered with operational amplifiers and mitigation actions are explained. For adequate tracking during production and operation, quality assurance methods were applied. This paper describes the steps taken to ensure radiation hardness compatibility of vacuum gauge electronics for the HL-LHC era.
Speaker: Nikolaos Chatzigeorgiou (CERN) -
15:00
Results from tests of the Ignite32/64 ASICs in CMOS 28-nm technology 20m
The INFN IGNITE project plans to implement a large-area ASIC (order 1-2 cm2) aimed at fast 4D-tracking. System pixels are required to have pitch below 50 µm and time resolution better than 30 ps. In the present paper we present measurement results concerning the performance of the two prototype ASICs, the Ignite32 and the Ignite64, designed to readout respectively 32x32 and 64x64 pixel matrices having 55 µm pitch, developed within the AIDAInnova initiative. The internal architecture of the ASICs, their modular concept and tested performance on time resolution are illustrated in this work.
Speaker: Adriano Lai (Universita e INFN, Cagliari (IT)) -
15:00
SALSA1 20m
SALSA1 is a test chip preparing the SALSA design, a reconfigurable readout ASIC for MPGD detectors designed in TSMC 65 nm. SALSA1 includes different analogue, mixed and digital blocks to be tested to evaluate the best options for SALSA. The chip is highly reconfigurable to adapt to a large diversity of situations, managing different gains, polarities and different peaking times, expected to reach up to 100kHz counting rates. Two different analogue channels and two different ADC, producing four configurations, are tested. The tests on the chip, received in January 2025, gave valuable insights to compare those configurations.
Speaker: Béatrice Guénégo -
15:00
SALSA: a new versatile ASIC for the readout of MPGD detectors 20m
The SALSA chip will be a versatile ASIC designed for various MPGD applications, including TPCs, trackers, and photon counting. It will feature 64 channels with tunable front-ends and fast ADCs, and a configurable DSP for data correction and feature extraction. The frontend includes a high open loop gain CSA, a pole-zero cancellation circuit, and a shaper, with four dynamic ranges and eight peaking times. Four ASIC prototypes have already been designed and tested to validate the main analog building blocks of the future SALSA chip: analog channel, ADC, PLL, analog and digital probes, I2C, etc.
Speaker: Dr Olivier Gevin (Université Paris-Saclay (FR)) -
15:00
Study of on-chip artificial neural network for incident angle classification 20m
The luminosity upgrade in high-energy physics experiment means large amount of data need to be processed and transferred. It brings challenges for design of vertex detectors both on the power consumption and readout rate. Our groups try to implement the compact data pre-processing module and artificial neural network into CMOS Monolithic Active Pixel Sensor (MAPS) to remove clusters generated by beam background and reduce the data load of system. The compact pre-processing algorithm and ANN model have been deployed in offline method, with validation conducted through MAPS beam test datasets.
Speaker: Ruiguang ZHAO -
15:00
The fabrication of the half-cylinder-shaped 10 Gb/s signal and flexible printed circuit power and data cable for ALICE ITS3 20m
The ALICE ITS3 upgrade at CERN replaces the innermost vertex detector layers with six self-supporting, half-cylinder MAPS sensors.
This concept introduces new electrical and mechanical challenges addressed by a custom flexible printed circuit (FPC). The FPC distributes eight 10.24 Gb/s signals, control lines, and five power supplies for 24 segments, enables a semi-cylindrical transition, and bridges millimeter- to micrometer-scale pitches. Built from three laminated sub-circuits over six layers, it is shaped via high-temperature, high-pressure molding. A Python-controlled, motorized bonding tool enables precise micro-wiring on curved surfaces. This work presents the FPC’s design, production, and integration into the ITS3 system.
Speaker: Marc Alain Imhoff (Centre National de la Recherche Scientifique (FR)) -
15:00
TID reliability of voltage translators for the ATLAS muon trigger system 20m
We studied the Total Ionizing Dose (TID) response of LSF0102 2-channel voltage translators intended for the upgrade of the ATLAS Muon Barrel read-out system for HL-LHC. TID tests were carried out at the CERN CC60 facility using a 60Co gamma source. The devices showed no degradation in key performance metrics, including supply current, eye diagram quality, rise/fall time, jitter, and bit error rate, up to the ATLAS-recommended dose. Results of a second irradiation at 20 kGy are under evaluation, with additional analysis using impedance spectroscopy modelling and techniques to assess potential degradation of specific device sections.
Speakers: Sabrina Perrella (Sapienza Universita e INFN, Roma I (IT)), Yasuyuki Horii (Nagoya University (JP)) -
15:00
Towards Enhanced Timing for Mu3e: The Ultra-Fast Silicon Pixel Detector 20m
We present the development of an Ultra-Fast Silicon Pixel Detector (UFSPD) for Phase II of the Mu3e experiment, which aims to detect the rare decay of a muon into three electrons. To achieve the required sensitivity of $10^{−16}$, enhanced time and vertex resolution are essential. The UFSPD should replace the Phase I SciFi detector and targets a time resolution of ~100 ps. The first test sensor, Picopix, built in 180 nm HV-CMOS, includes low-power pixels and integrated TDCs. Initial measurements show a TDC resolution of 56 ps RMS and sensor-level time resolution down to 200 ps RMS.
Speaker: Ivan Peric (KIT - Karlsruhe Institute of Technology (DE)) -
15:00
Using Open Source EDA Tools in ASICs for HEP: A mixed comparison 20m
Open-source design tools can play a very important role in the High-Energy Physics community. These tools offer a cost-effective alternative to proprietary EDA software, promoting reproducibility, collaboration, and long-term accessibility. This work presents a mixed comparison of three blocks — a Common-Mode Noise Filter (CMNN), Finite State Machine (FSM), and a VCO — designed using an open-source flow and synthesized for the IHP 130 nm open PDK where both the CMNN and the VCO were successfully taped out. A comparison of open-source and commercial design environments is also done, highlighting performance trade-offs, and their potential impact on the ASIC design.
Speaker: Felipe William da Costa (Polytechnic School of University of São Paulo) -
15:00
Wafer-Scale On-Chip Data Transmission for ALICE ITS3 MOSAIX Chip 20m
The ALICE ITS3 project develops a wafer-scale monolithic stitched pixel detector chip of 27~cm lengths. One of the main challenges in such a design is to transmit data from the 144 pixel matrices (or tiles) to the Left End-Cap (LEC) region where the readout processor is located, without compromising power consumption, noise coupled into front-ends, and the active pixel area. This contribution presents data transmission schemes implemented in the first stitched wafer prototypes (MOSS and MOST), and a new design approach based on differential, low-voltage swing for wafer-scale on-chip data transmission that significantly improves the performance of the previous implementations.
Speaker: Joao De Melo (Brookhaven National Laboratory (US))
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ASIC MEGAS ALEXANDROS Aquila
MEGAS ALEXANDROS Aquila
Conveners: Angelo Rivetti (INFN - National Institute for Nuclear Physics), Angelo Rivetti (Universita e INFN Torino (IT)), David Gascon (University of Barcelona (ES))-
15:20
A pixel readout chip prototype in 28 nm CMOS for time resolution study 16m
Dephy is a research and development project supported by the IN2P3 institute, aiming to investigate the technologies required for the development of small-pixel detectors for trackers in future particle accelerators. Among its objectives, the project focuses on designing pixel readout circuits with high timing resolution, capable of operating in extreme radiation environments. For timing-critical applications, the 28 nm CMOS process is of particular interest, as it enables the development of fast pixel designs while offering proven radiation tolerance. The design of the first pixel array prototype will be presented, and its test results will be shown and discussed.
Speaker: Mohsine Menouni (Aix Marseille Univ, CNRS/IN2P3, CPPM, Marseille, France) -
15:40
28 nm MOS Transistor SPICE BSIM Model for Simulating Electrical Effects of 1-Grad Total Ionizing Dose based on Gate Oxide Capacitance 16m
There are no existing SPICE models that account the effects of radiation doses exceeding 1 GRad in global transistor-level simulations for analog design in 28 nm CMOS technology within Electronic Design Automation environments. We present RAD-BSIM, the first SPICE model based on Berkeley Short-channel IGFET Model (BSIM) leveraging gate-oxide capacitance variations to enable robust circuit design up to 1 GRad. RAD-BSIM translates the effect of radiation-induced charge trapping at gate oxide, spacer, and shallow trench isolation layers into an equivalent variation in gate oxide capacitance. The model’s accuracy is validated by comparing RAD-BSIM simulated electrical characteristics with corresponding experimental measurements.
Speaker: Luca Gelmi (INFN section Milano-Bicocca and University of Cagliari) -
16:00
A 32-Channel Cryo-CMOS Readout ASIC for SNSPD Arrays with Sub-10ps Timing 16m
Superconducting nanowire single-photon detectors (SNSPDs) are promising candidates for novel particle detectors offering picosecond timing resolution, but are difficult to scale to large arrays. We present a 32-channel cryo-CMOS ASIC, fabricated in a 22nm FDSOI process, designed for tight integration with SNSPDs and operation at 4K. The ASIC targets 8.0ps RMS timing accuracy across 32 channels and includes on-chip bias generation, low-noise amplifiers, high-resolution time-to-digital converters (TDCs), and serializers for interfacing with room-temperature electronics. Measuring 4.0mm × 1.0mm, the ASIC addresses the challenge of scalable SNSPD readout. Initial results using a Caribou-based DAQ system will be presented.
Speaker: Davide Braga (FERMILAB)
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Systems AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Ken Wyllie (CERN), Sophie Baron (CERN)-
15:20
The readout electronics of the CMS MTD Barrel Timing Layer 16m
The MIP Timing Detector (MTD) is a key component of the CMS Phase-II upgrade for the High-Luminosity LHC. It includes a barrel (BTL) and endcap (ETL) timing layer. The BTL uses LYSO:Ce scintillating crystals coupled to SiPMs, read out by TOFHIR2 ASICs. The system targets a time resolution of 30 ps at the start of HL-LHC operation, degrading to 60 ps by the end due to radiation damage. We present an overview of the BTL readout electronics design and recent results from testing the production version of the TOFHIR2 ASIC and full system integration tests.
Speaker: Alessio Boletti (LIP, Lisboa (PT)) -
15:40
The RFSoC-Based Electronics Readout System for the BULLKID-DM Experiment: Sub-GeV Dark Matter Detection with MKIDs 16m
The BULLKID-DM experiment targets the detection of sub-GeV WIMP-like dark matter candidates using microwave kinetic inductance detectors (MKIDs). The experiment foresees the use of over 2000 individually instrumented silicon dice distributed across 15 wafers. We present the architecture of the room-temperature DAQ system based on the ZCU216 RFSoC board, including the design of a custom analog front-end board, an FMC+ interface card for the energy calibration system, and the design of the active veto detector. We also present the FPGA firmware for tone generation, frequency demultiplexing, system calibration, and triggering. Preliminary data from the demonstrator system will be presented.
Speaker: Luis Ardila-Perez (Institute for Data Processing and Electronics (IPE), Karlsruhe Institute of Technology (KIT)) -
16:00
Commissioning and operation of CGEM-IT readout chain 16m
A full readout chain based on TIGER, a triggerless ASIC, and on GEMROCs, ARRIA-V FPGA-based readout modules, has been deployed for the BESIII CGEM-IT detector, along with ancillary modules to connect with the pre-existing DAQ.
The full system was installed in the experimental hall at the end of 2024 and it is now being commissioned with the detector with cosmics and beam collision. A dedicated DAQ based on the GUFI interface has been developed waiting for the finalization of originally planned optical links readout.
The presentation will discuss the system and the experience working with it in the BESIII experiment.Speakers: Michela Greco (INFN - National Institute for Nuclear Physics), Michela Greco (INFN-UniTO)
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Break 30m
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17:40
InvitedConvener: Alex Kluge (CERN)
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16:50
Eyes on the Beam: Instrumentation for Measuring and Monitoring CERN’s Accelerators 45m
The success of CERN experiments depends on stable, high-quality beams, which require precise monitoring and control. In this talk, we will explore key beam parameters, the detectors and technologies that enable their measurement, and examples of the performance achieved across CERN’s accelerators. We will also discuss the challenges faced by the electronics and the additional demands posed by future accelerator projects, highlighting how the CERN Beam Instrumentation (BI) R&D roadmap is addressing these challenges to shape the next generation of beam measurement and monitoring technologies.
Biography
Andrea Boccardi is an electronics engineer specialized in digital acquisition systems and digital processing. He first joined CERN in 2001, working on the electronics for silicon detectors for the experiments in roles ranging from student to associate and fellow. After a short period in industry, he returned to CERN in 2006 on the accelerator side, joining the Beam Instrumentation Group (BI), where he still works today. Over the years, he has worked on a variety of instruments, and he currently serves as the leader of the Beam Position (BP) section, which is responsible for the design, development, and maintenance of beam position monitors across the entire CERN accelerator complex.Speaker: Andrea Boccardi (CERN)
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ASIC MEGAS ALEXANDROS Aquila
MEGAS ALEXANDROS Aquila
Conveners: Angelo Rivetti (Universita e INFN Torino (IT)), Angelo Rivetti (INFN - National Institute for Nuclear Physics), Marcus Julian French (Science and Technology Facilities Council STFC (GB))-
17:40
A novel scalable sub-picosecond TDC architecture based on free running oscillator 16m
This work presents the results of proof-of-concept ASIC implementing a novel TDC based on Time-to-Amplitude Converter (TAC) architecture demonstrating a best-case precision of 0.83 ps in a compact area (~0.021 mm²) and with low power (~2.6 mW per channel) making it suitable for high-density integration, typical of HEP applications.
It performs a time interval measurement between events by sampling a periodic signal, obtained by interpolating the nodes of a free running oscillator.
It demonstrates a worst-case precision of 1 ps for time intervals up to 3 ns and 3.68 ps up to 25 ns, with 1.79 LSB peak-to-peak INL.Speaker: Luca Iodice (Universite de Geneve (CH)) -
18:00
SPIDER ASIC for LHCb ECAL Upgrade II (PicoCal) 16m
We present the design and first test results for SPIDER_v0, the first ASIC prototype in CMOS TSMC 65nm designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements are a time resolution of 15ps, and an occupancy up to 30% (12 Mevent/s).
SPIDER_v0 is a 2-channel waveform digitizer allowing time reconstruction by digital algorithms. The architecture is based on 2 DLLs controlling the sampling window and sampling frequency, 8 banks of 32 analogue memory cells per channel and Wilkinson A/D conversion at 5 GHz for parallel digitization with a maximal conversion time of 200ns.Speaker: Baptiste Joly (LPCA Clermont)
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Integration, Interconnect and Packaging AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Francois Vasey (CERN), Ioannis Kopsalis (National Technical Univ. of Athens (GR)), Mr Ioannis Kopsalis (University of Birmingham (GB))-
17:40
Electro-mechanical integration of the ALICE ITS3 power and data distribution. 16m
During LHC Long Shutdown 3, ALICE will replace its innermost three tracking layers with wafer scale stitched Monolithic Active Pixel Sensors(MAPS) bent around the beam pipe. Each 27 cm-long sensor is connected via wire bonds to a custom three-layer Flexible Printed Circuit(FPC). These FPCs deliver power, transmit up to 40 high-speed(10 Gb/s) data and control signals. Designed for a half-cylindrical geometry and 100 µm ASIC pitch, they were optimised through simulations and electrical tests. Custom tooling enables precise bending and wire bonding. This contribution presents the design, integration, and assembly process of the ITS3 FPCs, highlighting technical challenges and solutions.
Speaker: Mr Antoine Junique (CERN) -
18:00
Development of in-house plating and hybridisation technologies for pixel detectors 16m
Reliable, cost-effective and scalable interconnect technologies are crucial for hybrid pixel detectors. Within the CERN EP-R&D programme and the AIDAinnova collaboration, a portfolio of single-die post-processing and hybridization techniques has been developed, especially suitable for small-volume productions. These include conductive adhesives (ACF and ACA) combined with in-house Ni/Au plating for fine-pitch hybridization down to 25 microns, as well as low-temperature gold-stud bonding with epoxy underfill for ~mm pitches. Connectivity yields up to 97% have been achieved on devices with 55 µm pitch and bonding areas up to 2 cm2 and up to 100% for large-pitch devices.
Speaker: Dr Ahmet Lale
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17:40
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21:30
Committee dinner
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10:00
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10:00
ASIC MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Conveners: Angelo Rivetti (INFN - National Institute for Nuclear Physics), Angelo Rivetti (Universita e INFN Torino (IT)), David Gascon (University of Barcelona (ES))-
09:00
High frame rate Skipper CCD-in-CMOS imaging array 16m
We present a Skipper-in-CMOS image sensor integrating Skipper-CCD non-destructive readout with CMOS pinned photodiode gain and in-pixel processing. Fabricated in a 180 nm process, a 200×200 array with 15×15 μm² pixels achieves 0.075e⁻ noise via multisampling. The SPROCKET2 ROIC, in 65 nm CMOS, supports 66.7 ksps high-speed readout with low DNL/INL and 10 μV resolution. A 20,000-pixel SPROCKET2 array with optical 10.24 Gbps links enables 4 kfps operation across 320,000 sensor pixels. We also demonstrate silicon photonic integration using microring modulators for 10.24 Gb/s optical output, enabling future detectors with tightly co-designed sensing, readout, and communication elements.
Speaker: Farah Fahim (Fermi National Accelerator Lab. (US)) -
09:20
On-Chip Data Transmission for Wafer-Scale MAPS 16m
Wafer-scale monolithic active pixel sensors (MAPS) for particle detectors face significant
challenges in on-chip data transmission due to high resistance and capacitance in CMOS
interconnects, leading to signal distortion, attenuation, dispersion, and inter-symbol
interference (ISI). This contribution outlines these issues in the ALICE ITS3 MOSAIX chip and
presents current solutions by implementing diJerential low swing transmission across
stitched tiles, achieving 160 Mb/s over ~12 mm and better performance compared earlier
stitched wafer prototypes (MOSS and MOST). As a future direction to push the performance
further, this work also highlights the Backbone Transmission Line Encoding (BTLE) Driver
system. This advanced solution, designed in same the technology as MOSAIX, uses a low-
power transmitter with digital pulse shaping, line coding, and polyphase FIR filtering to
mitigate ISI, enabling repeaterless 160 Mb/s links over 10 cm with a FoM of 37.3 fJ/bit/mm.Speaker: Joao De Melo (Brookhaven National Laboratory (US)) -
09:40
Front-end and sensor co-simulation methodology as a tool for design and characterisation of pixel detectors 16m
This contribution presents a co-simulation methodology that unifies sensor and front-end circuit modelling for pixel detectors. Traditional simplified signal models often fail to represent realistic particle-induced transients, leading to discrepancies between design-time assumptions and actual performance. The simulation chain enables simulation of a large number of realistic events, incorporating detailed signal shapes derived from TCAD and Monte-Carlo simulations into the analogue circuit simulation framework. This approach allows pre-silicon estimation of the influence of certain design choices on key metrics such as detection efficiency and timing performance, helping both front-end optimization and measurement interpretation of pixel sensors.
Speaker: Corentin Lemoine (CERN / IPHC-Strasbourg)
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Systems AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Csaba Soos (CERN), Sophie Baron (CERN)-
09:00
Sub-100 ps Timing Detector using FASTIC+ for SHiP experiment 16m
We report on the performance studies of the SHiP Timing Detector using the FASTIC+ front-end ASIC developed at CERN. The system is designed to achieve sub-100 ps time resolution to suppress combinatorial background in the SHiP experiment. Ongoing work includes comparative tests between FASTIC+ and a discrete electronics board, as well as studies with two scintillator types, EJ-204 and EJ-232. Laboratory tests with a picosecond laser and two dedicated beam campaigns in 2025 aim to evaluate time resolution, signal response, and material effects, guiding the final detector design and confirming FASTIC+ suitability for precision timing in high-rate environments.
Speaker: Gerardo Vasquez (University of Zurich (CH)) -
09:20
Comprehensive Full-Power Testing of Demonstrator System for the High Granularity Timing Detector 16m
The High Granularity Timing Detector (HGTD) is a timing detector designed to mitigate pile-up effects in object reconstruction, arising from increased luminosity in the ATLAS Phase-II upgrade. The demonstrator system is a prototype system incorporating all key components of the HGTD project, developed to validate critical aspects of system integration. Installation and commissioning of this demonstrator system has been on-going since 2024 and was fully equipped with 54 modules, enabling the execution of the full-power test. Performance of the modules and prototype electronics will be presented.
Speaker: Yimin Che (Nanjing University (CN)) -
09:40
Integration of a real-time FPGA tracking system in the LHCb DAQ chain 16m
The DoWnstream Tracker (DWT) is a system of interconnected FPGAs reconstructing, in the upcoming LHC Run 4, stubs of tracks from the LHCb tracking subdetector located downstream to the magnet (SciFi).
Based on the high parellisable architecture “Artificial Retina”, the DWT aims at accelerating the LHCb reconstruction in the High Level Trigger 1, implemented on GPUs, by injecting track “primitives” to speed up combinatorial tasks.
Presented here is the work on the DWT interface with the current LHCb DAQ chain, from the design to the tests performed at the LHCb Coprocessor TestBed facility.Speaker: Francesco Terzuoli (Università di Siena & INFN Pisa (IT))
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Break 30m
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11:15
InvitedConvener: Alex Kluge (CERN)
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10:30
Accelerator Technology Innovation for particle therapy 45m
A short introduction of the "MedAustron Cancer Treatment and Research Center" and the medical application of ion beams in radio therapy including a description of the MedAustron accelerator and instrumentation setup, based on the CERN PIMMS study, and its operation mode.
The talk will be concluded with an overview of research activities and technical developments to improve treatment modalities.Claus Schmitzer studied nuclear physics at the Technical University Vienna with a focus on quantum entanglement experiments of neutrons to test Bell inequalities. He then transferred to the "Hadron sources and Linac" group at CERN to follow up his PhD on a volume production H- plasma generator. Claus then joined MedAustron to take charge of the synchrotron RF system. After its successful installation and commissioning of the Synchrotron he took on MedAustron's "Physics" group responsible for Ion Sources and Linac/Synchrotron RF Systems. He went on to lead the AVID Group at MedAustron (Acceleration and Vacuum Technology, Ion Sources and Beam Diagnostics) covering a wide range of accelerator technology. Claus is now the head of MedAustron's Innovation Office within the accelerator development department.
Speaker: Dr Claus Schmitzer (EBG MedAustron)
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10:30
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LogicConveners: Andrea Boccardi (CERN), Prof. Johan Alme (University of Bergen (NO))
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11:20
Modular SystemVerilog-UVM Verification Environment for IGNITE Pixel Readout Chip 16m
Next‑generation pixel‑based read‑out ASICs for high‑energy physics experiments
face demanding performance and integration requirements. A flexible, pixel‑level
simulation framework is essential to design, validate, and optimize the read‑out
architecture and its building blocks. We present a SystemVerilog/UVM
verification environment developed for the IGNITE project, a 28 nm CMOS pixel
read‑out and processing ASIC designed for high‑intensity 4D‑tracking with $<10 \mu$m spatial and $< 50$ps temporal resolution in harsh radiation
environments. The verification environment comprises modular components for
configuration, parameterized random and cluster hit generation, and I/O
monitoring. Coverage analysis confirmed that all critical logic was thoroughly
exercised.Speaker: Ciro Fabian Bermudez Marquez (Universita e INFN, Bari (IT)) -
11:40
MOSAIX Qualification System for ALICE ITS3 16m
The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in high-energy physics. MOSAIX, a fully functional prototype and the final development step before production, measures 266 mm by 19 mm. The chip integrates 144 independently powered pixel matrices, eight 10 Gbps transmitters, and on-chip power and data distribution.
This contribution presents the development of the MOSAIX test system and verification strategy, with emphasis on validating the testing infrastructure before chip availability. The system includes an FPGA that controls MOSAIX and parses its output, and a second MOSAIX emulator FPGA.Speaker: Ola Slettevoll Groettvik (CERN) -
12:00
Analysis of Single Event Induced Bit Faults in a Deep Neural Network Accelerator Pipeline 16m
Recent advancements in Artificial Intelligence (AI) and AI hardware accelerators have paved the way for on-edge AI processing with many benefits such as reduced data bandwidth and increased power efficiency. Applications in harsh radiation environments could also benefit from these improvements. However, due to the complex nature of both accelerators and the AI models running on them, the effect of Single Event Upset (SEU) induced faults isn’t understood very well. This research aims to perform an in-depth analysis of SEU induced faults on an AI accelerator under different workloads to obtain information for implementing an efficient fault mitigation strategy.
Speaker: Mr Naïn Jonckers (KU Leuven - Magics Technologies)
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12:20
Radiation AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Hucheng Chen (Brookhaven National Laboratory (US)), Salvatore Danzeca (CERN)-
11:20
Upgrade of the ATLAS Tile Calorimeter Front-End Power Supply for the HL-LHC 16m
The Tile Calorimeter of the ATLAS experiment is being upgraded for the
high luminosity LHC. The powering scheme of the calorimeter modules has been updated to provide higher efficiency and redundancy. Switching power supplies used in each module are responsible for providing power to the front-end electronics. The original power supplies, which are currently being used in the detector, lack efficiency and radiation hardness for HL-LHC. Accordingly, many radiation tests have been performed and the design has been improved to provide higher efficiency and radiation tolerance.Speaker: Seyedali Moayedi (University of Texas at Arlington (US)) -
11:40
Multi-Gsps ADC radiation qualification for the LHC BPM system consolidation 16m
The consolidation of the Large Hadron Collider (LHC) Beam Position Monitor (BPM) requires digitising analogue signals from more than 1000 dual-plane BPMs using radiation-tolerant analogue-to-digital converters (ADCs). To this end, two commercial off-the-shelf (COTS) quad-channel, 12-bit ADCs operating at up to 1.6 Gsps were tested. Both ADCs were evaluated for cumulative radiation effects and single event effects (SEE) with a 200 MeV proton beam at Paul Scherrer Institute (PSI). This paper presents the radiation test results, assessing ADC performance and reliability under realistic operating conditions.
Speaker: Manoel Barros Marin (CERN) -
12:00
Radiation tolerance tests on key components of the ePIC-dRICH readout card 16m
The dual-radiator RICH detector of the ePIC experiment at the future Electron-Ion Collider will use more than 300 thousand SiPM pixels as photosensors, organized in more than 1000 Photodetector Units (PDU). Each PDU is a $\sim$5x5x12 cm$^3$ module that includes 4 custom ASICs, connected to 256 SiPMs, and a FPGA-based card (RDO) controlling the readout. Considering dRICH moderately hostile radiation environment, this work discusses the results of proton irradiation tests on key components of the RDO for radiation cumulative and single event effects. The tested components were validated for the RDO development, but SEU mitigation techniques are needed as expected.
Speaker: Mr Sandro Geminiani (University and INFN, Bologna (IT))
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11:20
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Lunch break 1h 20m
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13:40
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18:00
Social activity
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22:00
Conference dinner Athyvoles restaurant, Argiroupoli
Athyvoles restaurant, Argiroupoli
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10:00
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Logic AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES)), Prof. Johan Alme (University of Bergen (NO))-
09:00
"Unexpected talk" - GRAPH readout ASIC for large aperture, high resolution single photon imaging detectors designated for space applications 16m
Large aperture, high resolution, single photon imaging detectors are in high demand for future space explorations by missions
such as HABEX or LUVOIR. Yet making a TRL 10 operational detector prooved to be a very challenging endavour that takes more than
a decade. This talk will review the state of the art technology, and present more in depth an ASIC designed to cope
with the requierd operatioanl parameter space. To complement, some fresh results obtained operating the ASIC on the detector will be presented.Speaker: Andrej Seljak (Jozef Stefan Institute (SI)) -
09:20
Improving FPGA Timing Closure via Automated Pipeline Placement 16m
The growing capacity of high-end FPGAs enables more powerful algorithms in high-energy physics but introduces new challenges for firmware developers. The largest AMD devices, composed of multiple silicon dies (SLRs), face data transfer timing challenges due to Vivado’s placer limitations in large designs. In particular, pipelined buses crossing SLRs often experience poor flip-flop placement, impacting timing and latency. We present a Python tool that automatically generates optimized placement constraints for pipeline registers, equalizing propagation delays of the stages to improve timing closure while minimizing latency, number of pipeline stages, and resource utilization.
Speaker: Alvaro Navarro Tobar (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES)) -
09:40
EMP: A common infrastructure firmware framework for the CMS phase-2 upgrades 16m
In its phase-2 upgrades, all of the CMS experiment's backend electronics systems are being replaced by ATCA boards featuring AMD Xilinx UltraScale+ FPGAs and high-speed optical modules. The EMP (Extensible Modular data Processor) framework provides common infrastructural firmware components, top-level designs and associated software for multiple CMS phase-2 backend boards and systems. It implements and integrates high-speed serial link protocol engines, data capture and playback buffers, clocking components, and readout. In this talk, I will present an overview of all of the framework's key components, the associated build tooling and test suites, along with lessons learnt during the framework's development.
Speaker: Tom Williams (Rutherford Appleton Laboratory (GB))
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10:00
Modules MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Conveners: Andrea Boccardi (CERN), E. D. Kyriakis-Bitzaros-
09:00
Manufacture and QC of the ATLAS ITk quad pixel module flex PCB 16m
ITk hybrid pixel detector consists of about 10,000 planar “quad” modules formed from 4 ASICs, (developed within the RD53 collaboration) bump bonded to a single sensor.
The flexible PCB attached to the sensor connects the ASICs to the system and provides the module's electrical environment.
To guarantee long-term reliability in the harsh HL-LHC environment, a tight quality control is mandatory.
Using three bare flex and three population vendors the populated flexes are manufactured as per IPC standards,
Quality Control (QC) protocols were developed to maintain quality and maximise module yield.
We describe in detail the QC process and results.Speaker: Dr Richard Bates (University of Glasgow (GB)) -
09:20
Development of Time-of-Flight System for an Energetic Particle Spectrometer in Space 16m
We present the development of a 30 cm long Time-of-Flight (ToF) system targeting 30 ps timing resolution for charged particle detection. The system as part of a miniaturized charged particle spectrometer enables the extension of energy measurement to 2 GeV/n without using a magnet. Each of the two ToF channels integrate a plastic scintillator coupled to a silicon photomultiplier (SiPM), custom readout electronics, and a Constant-Fraction Discriminator (CFD). A Tapped-Delay-Line (TDL) Time-to-Digital Converter (TDC) with dynamic range of 2.5ns and LSB ~3.8ps implemented in FPGA digitizes the time difference between the trigger signals. A reference detector has been characterized.
Speaker: Yiannis Kazas (Nat. Cent. for Sci. Res. Demokritos (GR)) -
09:40
A two-stage time-stretching TDC with discrete components 16m
One of the main challenges of picosecond TDC for 4D pixel detectors at future hadron colliders is the limitations of power consumption (down to $\mu$W/channel). To significantly reduce the power consumption and maintain other key specifications such as trigger rate and time resolution, a two-stage time-stretching TDC is proposed. This talk will present the proof-of-concept prototype design and testing of such TDC with discrete components (such as SMT transistors and capacitors). Time resolution of better than 100 ps is achieved with a 100 MHz clock, making it a stepping-stone towards future ASIC design with modern CMOS technology.
Speaker: Yanbo Chu (Tsinghua University (CN))
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09:00
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Break 30m
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11:15
InvitedConvener: Francois Vasey (CERN)
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10:30
Readout Electronics System for the CEPC Reference Detector 45m
Abstract
The framework of the readout electronics system for the CEPC reference detector has been designed based on background simulations and the baseline design of sub-detectors. To maximize the possibility of new physics exploration, an architecture of front-end triggerless readout with a full back-end trigger has been chosen as the baseline. The detector front-end electronics will be mostly implemented with ASICs to the radiation tolerance requirements. Inspired from CERN common projects such as lpGBT, Versatile Link and bPol, a common data interface, realized by a chip-set FEDI (Front-End Data Interface ASIC), and a common power module PAL (Power At Load), will be used for all the sub-detector electronics. The back-end electronics can thus also benefit from this architecture, which features a unique interface protocol, and can be commonly designed for all sub-detectors. In this talk, we will introduce the overall design of CEPC sub-detectors electronics with their general requirements, the latest R&Ds, especially the ASICs and the common interface system. In the end, our research team will be introduced and the effort related to the DRD7 will be discussed.Biography
Wei Wei is a professor at the Institute of High Energy Physics (IHEP), Chinese Academy of Sciences, and the leader of the electronics group there. He graduated from the University of Science and Technology of China (USTC) with a bachelor's degree in Physics in 2005 and received his PhD from IHEP in 2010. Since then, he has been involved in ASIC design, especially in the areas of pixel detectors and waveform sampling. He has led the design teams for the Photon Counting pixel detector of HEPS (High Energy Photon Source), the Charge Integration pixel detector for SHINE (Shanghai High Repetition Rate XFEL and Extreme Light Facility), and the CMOS Pixel Sensor chip Taichupix for the CEPC Vertex detector. He is leading the development of the CEPC Electronics System, and the author/editor of the electronics chapter in the Technical Design Report for the CEPC Reference Detector.Speaker: Wei Wei
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Modules MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Conveners: Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES)), E. D. Kyriakis-Bitzaros-
11:20
PCIe400 generic readout board qualification test 16m
The data acquisition system of LHCb Upgrade I is a single stage readout followed by event building, real time reconstruction and selection. A generic readout board, called PCIe400, embedding Altera’s flagship Agilex 7 M-series FPGA with a 4x112 Gbit/s serial interface and a PCIe Gen 5 interface constitutes a baseline for LHCb future upgrades. It also targets clock distribution with phase determinism <10 ps pk-to-pk on 46 links. Presented here are results of qualification tests performed on prototype boards.
Speaker: Julien Jiro Langouët (Aix Marseille Univ, CNRS/IN2P3, CPPM, Marseille, France) -
11:40
OPTIMA, a board dedicated to Optimized Precision Timing for Multichannel Acquisition 16m
In the new era of HL-LHC experiments, fast-timing detectors are emerging as a critical priority. Typical requirements include a temporal hit resolution of ~50 ps, spatial resolution of ~12 $\mu$m, and radiation hardness up to 10$^{16}$ neq/cm$^2$. To address these challenges, the development of non-standard sensor designs and advanced fast-readout electronics is required. The OPTIMA multichannel board addresses the need for testing small sensor demonstrators, providing fast readout up to 16 channels and compatibility with test beam environments.
This contribution will present the design of the OPTIMA board, its integration in test beams and the first experimental results.Speaker: Federico De Benedetti (Universidade de Santiago de Compostela (ES)) -
12:00
Keeping the ATLAS ITk cool and dry 16m
The ATLAS Inner Tracker (ITk) will begin operation at the HL-LHC following LS3 for Run 4. Humidity inside the detector will be monitored using radiation-hard Fiber Optic Sensors based on Long Period Grating (LPG) and Fiber Bragg Grating (FBG), designed to operate below -20 °C and <10% humidity. Measuring relative humidity requires a complex method involving independent temperature and radiation dose readings at each sensor location. An optical interrogator captures the reflection spectrum, revealing characteristic peaks. This contribution presents the most effective method for extracting relative humidity, including spectral filtering to achieve 10 pm resolution.
Speaker: Xola Gugulethu Mapekula (University of Johannesburg (ZA))
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12:20
Power AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Hucheng Chen (Brookhaven National Laboratory (US)), Magnus Hansen (CERN)-
11:20
Grounding and shielding strategy, validation and testing for the ATLAS ITk Pixel Outer Barrel 16m
For the ATLAS Inner Tracker Pixel Outer Barrel, robust grounding and shielding (G&S) are critical to ensure the required detector performance. This contribution presents the G&S strategy developed to avoid ground loops, enhance common-mode noise rejection, and maintain shielding integrity for the pixel modules. Results from electromagnetic compatibility (EMC) testing of the first pre-production Loaded Local Support (LLS) are reported. Noise sensitivity to injected electric and magnetic fields and common-mode disturbances on power lines is quantified. Furthermore, G&S verification method and overall strategy for detector integration, including the use of the Ground Fault Monitor system, are discussed.
Speaker: Susanne Kuehn (CERN) -
11:40
Performance Evaluation and Mass Production Readiness of the CMS Low Voltage Power Supply: Radiation, Magnetic Field, and Environmental Tests. 16m
The Low Voltage Power Supply is a modular power converter stepping down 380VDC to 12VDC to power the widely used bPOL12V point-of-load converters. It is designed to operate in the radiation and magnetic-field environment of the CMS towers of experimental cavern. Three prototype iterations underwent radiation and magnetic-field testing, followed by progressive technical qualification. We present the environmental test methodology and summarize results from the latest irradiation and magnetic-field test campaigns. Key performance metrics, like conversion efficiency, output voltage stability, over-current and over-voltage protection, interlock behaviour - are evaluated against the requirements, aiming at proofing production readiness.
Speaker: Krzysztof Stachon (University of Zurich (CH)) -
12:00
Development, testing and validation of the CMS-HGCAL low-voltage powering chain 16m
The low-voltage supply chain for the High Granularity Calorimeter (HGCAL) Phase-2 upgrade of CMS powers the front-end electronics of 620m2 of silicon sensors and 370m2 of SiPM-on-Scintillating tiles. This chain consists of Low-Voltage Power Supplies custom-developed by CMS to operate in the experimental cavern, that power bPOL12V-based DCDC converters located inside the experiment, and custom low-dropout linear regulators as Point-Of-Load regulation. This work presents the design details, the electrical characteristics and the system integration challenges. Experimental tests are presented to evaluate the static and transient performance of the full powering chain and its impact on the front-end modules.
Speaker: Pablo Daniel Antoszczuk (CERN)
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11:20
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Lunch break 1h 10m
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13:30
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15:20
Links & FPGA User Group AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Francois Vasey (CERN), Ken Wyllie (CERN), Salvatore Danzeca (CERN)-
13:30
IMEC silicon photonic platforms for advanced PICs 30mSpeaker: Muhlam Khoder (IMEC)
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14:00
Versatile Link Plus project status 20mSpeaker: Csaba Soos (CERN)
- 14:20
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14:50
FPGA irradiation campaign in ATLAS cavern 20mSpeaker: Daisuke Hashimoto (Nagoya University (JP))
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15:10
Discussion 10m
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15:20
Microelectronics User Group MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Convener: Kostas Kloukinas (CERN)-
13:30
CERN ASIC support and Foundry services News & Discussion (40') 40mSpeakers: Kostas Kloukinas (CERN), Marco Andorno (CERN)
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EUROPRACTICE IC services and Foundry news (25') 25mSpeakers: Paul Malisse, Paul Malisse (IMEC)
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EUROPRACTICE EDA tools for the HEP community (25') 25mSpeaker: Mark Willoughby
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15:10
Discussion 10m
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Modules MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Conveners: Andrea Boccardi (CERN), Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))-
15:20
The CMS Barrel Calorimeter Processor production candidate (BCPv2) board evaluation 16m
The Barrel Calorimeter Processor (BCP), based on ATCA blade architecture, has been developed for the readout of the electromagnetic calorimeter (ECAL) and hadron calorimeter (HCAL) subdetectors. The BCP supports 120 optical receive channels of up to 25 Gbps, 72 optical transmit channels of up to 25 Gbps, an AMD XCVU13P UltraScale+ FPGA, and an embedded AMD Zynq UltraScale+ SoC. The production candidate BCP V2 is currently undergoing testing. This presentation highlights key testing results, such as high-speed link performance, power integrity, and clock phase alignment, as well as lessons for the design of the upcoming production BCP V3.
Speaker: Stephen Goadhouse (University of Virginia (US)) -
15:40
A Low-Power LGAD–Timepix Dosimeter for Biological Space Radiation Monitoring 16m
ALCYONE, an EU-funded project under the Horizon Europe program, addresses the impact of prolonged space exposure on biological systems, which is a critical challenge for future long-duration space missions. The project focuses on the development of a miniaturized on-chip micro-incubator to monitor and control environmental conditions for four types of cell cultures. To ensure precise radiation monitoring, a novel high-resolution dosimeter based on fine-pitch trench-isolated LGADs, coupled with Timepix front-end chips, has been developed and will be presented. The detector is seamlessly integrated into a compact, high-performance system-on-chip platform, enabling real-time processing of radiation fluence and dose.
Speaker: Dr Michele Caselle (KIT - Karlsruhe Institute of Technology (DE)) -
16:00
FPGA-Based Real-Time Waveform Classification and Reduction in Particle Detectors 16m
The SHiP SBT self-triggered readout will process SiPM sum signals sampled at 800 MSPS and 12 bit resolution to extract calorimetric particle hit information.
A waveform classification is being deployed on the readout FPGA to reduce the volume of transmitted data. The classification divides events into expected signal, expected noise or containing unexpected features applying different degrees of compression. In this study, we consider LUT-based neural-networks and address challenges of NN layout, footprint and performance.
Preliminary planning indicates significant data reduction, easing constraints on infrastructure.Speaker: Dr Ilja Bekman (Forschungszentrum Juelich GmbH (DE))
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Trigger AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Mr Ioannis Kopsalis (University of Birmingham (GB)), Ioannis Kopsalis (National Technical Univ. of Athens (GR)), Sophie Baron (CERN)-
15:20
From Discrete Components to ASICs: Achieving Sub-Picosecond Clock Synchronization for Large-Scale Detectors 16m
We present an implementation of the digital dual mixer time difference (DDMTD) circuit in an ASIC using current mode logic (CML) and discuss how it can be used to stabilize on-detector systems to a level of less than 1 picosecond. This circuit is used extensively in high energy physics applications and other clock distribution systems to monitor clock stability using FPGAs. By using CML logic in an ASIC we have been able to optimize the design for the DDMTD application and have achieved a considerable performance enhancement over what has been achieved with logic blocks in an FPGA.
Speaker: Rohith Saradhy (University of Minnesota (US)) -
15:40
Precision Timestamping Methods for ECAL Upgrade II on Front-End FPGA 16m
Precision timing is critical for the LHCb ECAL Upgrade II to operate effectively in the high pile-up conditions of the HL-LHC. Fast waveform sampling ASICs have been identified as suitable readout electronics for achieving the few tens of picoseconds resolution required to reconstruct electromagnetic showers. To extract precise timestamps in the presence of pile-up induced background, machine learning-based methods have been developed to predict the time of arrival of analog waveforms. This machine learning model has been optimized and deployed on a Xilinx Artix-7 FPGA for testing and can be translated to radiation-tolerant PolarFire FPGAs for future ECAL integration.
Speaker: Lauren Mackey (Syracuse University (US)) -
16:00
Assessing the performance of future White-Rabbit RF and Timing distribution system for LHC under real conditions 16m
To meet the High-Luminosity LHC demand for enhanced phase stability and replace the outdated RF and timing distribution system (called TTC backbone), an upgrade to a White Rabbit-based system is planned. A compliance test showed a phase variation of less than 30 ps in a proof-of-concept system. In order to assess the quality of the new system in real conditions a test campaign was started in several points of LHC monitoring its phase stability with respect to the RF-master frequency and comparing it to the TTC backbone currently in operation. The test campaign will be described and results presented.
Speaker: Lilith Kaffka (CERN)
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Break 30m
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InvitedConvener: E. D. Kyriakis-Bitzaros
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16:50
Designing ASICs for HEP Experiments: Turning painful mistakes into practical guidelines for future ASICs in HEP 45m
ASICs are now indispensable in High-Energy Physics, powering everything from ultra-low-noise front ends to high-speed data aggregation under extreme radiation. But designing them for detectors is nothing like commercial chip development: every project is unique, resources are thin, and mistakes often surface only after tapeout or production.
This talk looks at the pitfalls we’ve encountered—broken analog models, incomplete verification coverage, unexpected power density issues, and specifications that evolve faster than the chips themselves. More importantly, it distills these hard lessons into practical guidelines: adopt Digital-on-Top flows, validate models as rigorously as designs, design for verifiability and testability, and plan for specifications that will change.
The goal is simple: to help future HEP ASIC projects avoid repeating past mistakes, and to move from fragile, one-off developments toward sustainable engineering practices that still leave room for innovation.
Bio – Davide Ceresa
Davide Ceresa is an electronics engineer at CERN specializing in microelectronics and digital ASIC design for high-energy physics applications. He earned his Ph.D. in Electronic Devices through a joint POLITO–CERN program, focusing on intelligent particle tracking systems. Previously, he completed a Master's in Nanotechnologies for ICTs (POLITO–INPG–EPFL) and a Bachelor's in Physics Engineering (POLITO).Since joining CERN in 2012, Davide has played key roles in designing, testing, and producing custom integrated circuits for particle detectors. As the main designer of the CMS Outer Tracker MPA chip, he led its development from concept to industrial production and testing. He also served as ASIC working group convener for the CMS Outer Tracker Phase-II upgrade.
Currently, Davide serves as deputy leader of the CERN EP R&D work package on IC technologies. In this role, he defines research priorities, leads design and testing teams, and guides technology development for next-generation detectors. His work bridges the gap between research and application, bringing advanced ASIC methodologies—such as Digital-on-Top flows and radiation-tolerant design—to the HEP community.
Beyond his technical work, Davide mentors colleagues, supports projects through the CHIPS program, and champions best practices in ASIC development to strengthen the long-term sustainability of HEP microelectronics.
Speaker: Davide Ceresa (CERN)
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19:00
Poster 2 Athina hall
Athina hall
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Development of a Central Trigger Processor board for the Advanced SiPM based camera of the CTA Large-Sized Telescopes 20m
We present ongoing work on a Central Trigger Processor (CTP) board for the future Advanced SiPM-based LST camera of CTAO (Cherenkov Telescope Array Observatory). The system aims to implement a fully digital trigger on FPGAs, leveraging increased camera resolution to better discriminate low-energy gamma-ray events from noise. This approach seeks to enhance sensitivity while meeting CTAO-LST’s strict timing and data rate requirements. The CTP is also intended to provide hardware-level stereo triggering among LSTs. We will describe the conceptual design and current status of the CTP development, along with initial prototypes under evaluation as part of this advanced trigger architecture.
Speaker: ALEJANDRO PEREZ AGUILERA Not Supplied -
17:55
The Phase 2 Global Trigger / BRIL ATCA Rear Transition Module 20m
For the Phase-2 Upgrade of the CMS Level-1 Trigger, a dedicated ATCA Rear Transition Module for the Serenity ATCA blade has been designed. It is intended to be used by the Phase-2 Global Trigger as well as the Beam Radiation Instrumentation and Luminousity group during operations of the CMS detector. It acts as a generic port expander for the Serenity card and is responsible for signal translation between Samtec Firefly and SFP, handling galvanic in and outputs used as clock and data lines as well as providing additional SFP connectivity.
Speaker: Elias Leutgeb (Technische Universitaet Wien (AT)) -
18:15
The iFTDC Front-End Card for the COMPASS and AMBER Experiments 20m
The iFTDC is a low cost, simple and flexible front-end card designed to measure signal timing for different types of detectors with a precision of 150 ps. It's based on ARTIX-7 FPGA, has 64 LVDS inputs and few user IO pins for configuration of attached ASICs. The FPGA's built-in high-speed serial link connects the board to the DAQ using the Unified Communication Framework protocol. The iFTDC can be connected directly to Ethernet for laboratory measurements. The iFTDC firmware has built-in scalers and can be operated in streaming mode.
The performance and applications of the iFTDC cards are discussed.Speaker: Igor Konorov (Technische Universitaet Muenchen (DE)) -
18:35
Implementation of ML based conditions for the Phase-2 CMS Global Trigger upgrade 20m
The new CMS trigger system for the High-Luminosity LHC upgrade will exploit detailed information from the sub- detectors at the bunch crossing rate, allowing the Global Trigger (GT) FPGA firmware to use high-precision trigger objects. The GT will contain novel algorithms based on machine learning techniques such as Deep Neural Networks and Boosted Decision Trees to reach higher selection efficiency on particular event signatures. This study focuses on optimizing these models through techniques like quantization and pruning, with an emphasis on integrating high-level features, such as invariant mass and ∆R, already computed in firmware, into the existing ML models.
Speaker: Gabriele Bortolato (Universita e INFN, Padova (IT)) -
18:40
512-Channel SiC Beam Monitor Electronics: Single-Particle up to Clinical Beam Rates Using Commercial Components 20m
A 512-channel beam monitor was developed to measure beam parameters at particle rates from single particles up to clinical rates (several GHz). The system is designed for silicon carbide (SiC) strip sensors for increased radiation tolerance. The sensor readout uses four 128-channel analog charge-integrators with on-chip multiplexers, complemented by ADCs and a SoC module (FPGA + CPUs). Gigabit Ethernet, an SFP+ interface, and electrical and optical links enable communication with auxiliary systems. The system operates from a single power supply and was implemented on a 426×253 mm², 12-layer PCB. All components, except for the sensors, are commercially available.
Speaker: Richard Thalmeier (Austrian Academy of Sciences (AT)) -
18:40
A High-Granularity, Ultra-Fast Detector System for Nuclear Resonance Scattering Experiment 20m
LANRS (Exploration of Lattice Dynamics of Nanostructures and Active Site Structures in Iron Proteins and Batteries with Nuclear Resonance) is a ministry-funded project aimed at enabling next-generation Nuclear Resonance Scattering (NRS) experiments. These require a large detection area, ultra-high temporal resolution of a few nanoseconds, and the ability to handle high event rates immediately after beam interactions. We present a novel detector concept addressing these needs, based on multiple Timepix3 front-end chips coupled with a high-resolution, ultra-fast sensor that leverages trench-isolated Low Gain Avalanche Diode (LGAD) technology.
Speaker: Mr Nour Sharif (KIT - Karlsruhe Institute of Technology) -
18:40
Advancements and future expansions of the Caribou DAQ system 20m
Caribou is a versatile data acquisition system developed for use in several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It combines a custom Control and Readout (CaR) board with a Xilinx Zynq System-on-Chip (SoC) running project-wide shared firmware and software stacks. Ongoing migration to Zynq UltraScale+ platforms aims to integrate SoC functionality directly into the CaR board, enhancing system performance and compactness. This contribution introduces the Caribou system and outlines recent progress across its hardware, firmware, and software components.
Speaker: Younes Otarid (CERN) -
18:40
Advancements in a Test Stand for Inner System Electrical Links of the ATLAS Inner Tracker (ITk) Upgrade Silicon Detector 20m
Over the past year, significant progress has been made in the development of a dedicated test stand designed to evaluate the signal transmission integrity of approximately ~9k electrical links used in the Inner System (IS) of the ATLAS Inner Tracker Pixel upgrade. The Quality Control (QC) method of choice is a pre-existing multi-channel FPGA data acquisition architecture that has the capability of producing Bit Error Rate (BER) tests and virtual eye diagrams at a data rate of 1.28Gb/s. This presentation includes the developments in the calibration of the QC infrastructure and results from multiple IS pre-production bundles.
Speaker: Austin Mullins (Southern Methodist University (US)) -
18:40
An Highly Integrated Detector Readout Module for Fast Prototyping Using RFSoC 20m
We present a flexible detector readout prototyping module based on the AMD RFSoC platform, integrating fast ADCs, DACs, programmable logic, multicore CPU and several 28 Gbps-class transceivers. Sampling at GHz rates enables full digital signal processing, simplifying analog front-ends and improving timing and compactness. Two use cases are demonstrated: a digital emulation for the NA62 Liquid Krypton Calorimeter trigger and readout chain, and early prototyping of readout electronics for the EPIC MPGD Endcap Tracker. This approach accelerates development and co-design of detectors and front-end electronics, paving the way for scalable and customizable DAQ systems in high energy physics.
Speakers: Alessandro Marcelli (INFN Roma Tor Vergata), Roberto Ammendola (INFN e Universita Roma Tor Vergata (IT)) -
18:40
An overview of the hardware trigger system for the drift chamber of Belle II 20m
The Belle II experiment is a collider experiment using asymmetrically accelerated electrons and positrons with the world's highest luminosity.
The experiment uses a hardware trigger system consisting of customized electronic boards called Universal Trigger and other electronics.
The trigger system has a dedicated subsystem for the drift chamber of the Belle II detector, which measures the trajectories of charged particles.
This subsystem comprises wire mergers, Hough transformers, noise filters, and neural networks to find trajectories in low latency, which operate on the FPGA of the Universal Trigger boards.
We introduce an overview of the sub-trigger system and its upgrade plan.Speaker: Hanwook Bae -
18:40
Building Complex SoC Images Made Simple with SoCks 20m
Modern System-on-Chip (SoC) devices are widely applicable; several boards in the LHC Phase-2 upgrade use them. However, their growing complexity, along with the increasingly intricate firmware and software development tools, makes it difficult for developers to keep up. To address this, we propose SoCks, a modular and scalable build framework for SoC devices that introduces a new layer of abstraction and reduces dependencies wherever possible while making the remaining ones comprehensible. Unlike previous approaches, SoCks enables independent builds of the firmware and software components of the SoC image, maintaining clearly defined interfaces to ensure the essential flow of information.
Speaker: Luis Ardila-Perez (Institute for Data Processing and Electronics (IPE), Karlsruhe Institute of Technology (KIT)) -
18:40
C++ LpGBT control library for Accelerator Controls at CERN 20m
Reliable communication and control of distributed electronics is essential for safe and efficient accelerator operations at CERN. This work presents the first application of new C++ library designed to manage Beam Loss Monitoring (BLM) acquisition electronics using Low-Power Gigabit Transceivers (LpGBT). This library enables real-time communication between tunnel-based and surface-level processing subsystems, delivering high performance and robust reliability. It supports redundant optical links, custom medium access, internal and external LpGBT control, and I²C links. Although LpGBT is widely deployed in LHC experiments, this marks the first integration in CERN’s Accelerator Technologies sector, offering enhanced control capabilities via radiation-tolerant, bidirectional communication.
Speaker: Mathieu Saccani (CERN) -
18:40
Design of the ASIC readout scheme for the muon detector of CEPC experiment 20m
The Circular Electron Positron Collider (CEPC) has been proposed to operate as a Higgs factory producing electron-positron collisions with a center-of-mass energy of 240 GeV. The muon detector of CEPC plan to use the plastic scintillators with silicon photomultiplier (SiPM) to collect the scintillation light. In this work, we report the design of a readout system based on the ASIC readout scheme to handle the multi-channel from the SiPMs. A dedicated mockup system has been built and its performance are carefully evaluated. The testing results show that this system meets the requirements of the muon detector of CEPC.
Speaker: Jie Zhang (Institute of High Energy Physics, CAS, China) -
18:40
Design of the ATLAS ITk pixel module Quad flex PCB 20m
ITk hybrid pixel detector consists of about 10,000 planar “quad” modules formed from 4 ASICs, (developed within the RD53 collaboration) bump bonded to a single sensor operated in serial power chains.
The flex attached to the sensor connects the ASICs to the system and provides module electrical environment while fulling the mechanical specifications.
The flex must provide a signal transmission at 1.28Gbps, and a power domain that minimizes voltage drops. It must be low material to reduce radiation length and stress in the module bump bonds due to CTE mismatch.
We describe the design and design validation of the flex.Speaker: Sneha Amogh Naik (University of Glasgow (GB)) -
18:40
Development and Implementation of Non-Zero Suppression System for HGCAL 20m
In preparation for operations at the HL-LHC, the CMS Collaboration is upgrading its endcap calorimeters with a high granularity calorimeter (HGCAL). The HGCAL back-end electronics includes two Non-Zero Suppression (NZS) boards, which dynamically disable zero-suppression in designated regions of interest. This paper presents a detailed discussion of the NZS algorithm’s principal components, and a comprehensive account of the hardware testing performed on the Serenity 3 platform, including validation against a Python-based digital twin. The resulting system delivers 432-bit NZS flags, disabling zero suppression on the front-end sections, to each of the 48 DAQ (Data Acquisition) boards of one endcap.
Speaker: Berke Akgul (Yildiz Technical University (TR)) -
18:40
Development of an Array Silicon Drift Detector System for Synchrotron Radiation Applications 20m
To enhance solid-angle coverage and detection efficiency in synchrotron radiation experiments, the HEPS/PAPS Detector System Project Team at the Institute of High Energy Physics has developed prototype SDD array systems, consisting of 5 and 20 hexagonal-pixel elements, in response to the future requirements of the High Energy Photon Source (HEPS), a fourth-generation synchrotron facility currently under construction in China. The self-developed 20-unit array detector system, with complete development of the sensor, front-end ASICs, and readout electronics, has been tested using a 241Am source, achieving an energy resolution of 300 eV at 13.96 keV (-40 °C).
Speaker: Ziyu Bao -
18:40
Digital implementations of algorithms for charge sharing compensation in hybrid pixel detectors. 20m
Hybrid pixel X-ray detectors operating in single-photon counting mode provide high spatial resolution, enhanced spectral imaging, and immunity to electronic noise. A common trend is to minimize pixel size, however, it often comes at the expense of spectral fidelity and position resolution due to charge sharing between channels. The spatial resolution can be further improved, though, by analyzing the proportions of charge collected by neighboring pixels. This work focuses on a new digital algorithm that leverages charge sharing to detect event positions with subpixel resolution. Digital algorithms are modeled using the SystemVerilog and verified through simulations.
Speaker: Dr Aleksandra Krzyżanowska (AGH University of Krakow) -
18:40
EMCI–EMP: A Scalable, High-Performance Slow-Control Interface for the ATLAS Detector Control System 20m
The Embedded Monitoring Processor (EMP) is a state-of-the-art platform based on a multi-processing System-on-Chip, developed for the upgrade of the ATLAS experiment’s Detector Control System. The EMP interfaces via high-speed optical transceivers with monitoring and control functionalities of radiation-tolerant Front-Ends. Preliminary analysis revealed limitations in throughput and CPU efficiency using standard data transfer solutions between the Programmable Logic and the Processing System. Therefore, a custom DMA IP core is being developed to optimize throughput, reduce CPU load, and improve scalability. This contribution presents the modular firmware design and ongoing developments aimed at achieving a high-performance data path for slow-control data.
Speaker: Dominic Ecker (Bergische Universitaet Wuppertal (DE)) -
18:40
Flexible Data Readout Firmware for the CMS Phase-II Back-End Trigger Cards 20m
The upcoming Phase-2 upgrade of the LHC presents significant challenges for CMS Back-End electronics due to dramatic increase in trigger rate, data volume, and system complexity. The system must handle L1A rates up to 750kHz with a L1A latency of 12us. The EMP Common Readout firmware addresses these needs, as a modular and flexible system designed to unify trigger event data collection across CMS Back-End Phase-2 subsystems. This contribution presents the architecture and implementation of the EMP Common Readout, along with results from high-rate tests across multiple setups as well as beam test data-taking, with billions of events recorded.
Speaker: Stavros Mallios (CERN) -
18:40
Forward Feature Extractor for ATLAS Level-0 Trigger System Phase-II Upgrade 20m
The forward Feature EXtractor (fFEX), a new ATLAS calorimeter
first-level trigger subsystem, will extend ATLAS' trigger
performance for jets and electromagnetic signatures in the
Forward Calorimeter (FCal). Utilising the full calorimeter
granularity, each processor processes ~2.3 Tbps of real-time
data. It is part of the trigger upgrade for the challenging
conditions in the High Luminosity LHC (HL-LHC) phase, where
a significantly increased pile-up is expected.This presentation provides an overview of the hard-/firmware
design, results of the prototype's verification and highlights
fFEX's role in preparing ATLAS for the HL-LHC era.Speaker: Viacheslav Filimonov (Johannes Gutenberg Universitaet Mainz (DE)) -
18:40
Front-End card, a key element of the CMS ECAL readout chain: design-oriented tests, performance, quality control 20m
Abstract
Performance and stability of the CMS ECAL HL-LHC readout system depends on the good functionality of the Fron-End card (FE) – an interface between on-detector and off-detector section of the readout electronics.
Series of the design-specific integration tests were performed, including dependence of the readout chain functionality on the system clock quality, recovery from the clock loss and from the SEU etc. with the emphasis on the custom chips performance and possible limitations.
The quality assurance procedure was defined and implemented in the custom FE card test setup hardware and software.Speaker: Alexander Singovski (University of Notre Dame (US)) -
18:40
Future development of the telecom based modular computing architectures for high energy physics readout applications in post-telecom era. 20m
In the context of the HL-LHC upgrades, xTCA (Advanced/Micro Telecom Computing Architecture) is a common standard in high energy physics. To keep it is a serious candidate for future readout systems and save the previous development investments in the post-telecom era, when classical telecom vendors migrating to cloud-based solution, the new coordination with manufactures is required. PICMG (PCI Industrial Computing Manufacturer Group) reacts by revising ATCA family specifications to support next level of performance and scalability of modular computing modern application for non-telecom markets
Speaker: Mr Alexey Mitrofanov (Comtel Electronics GmbH) -
18:40
High precision X-ray beam stability adjustment verification platform based on the fourth generation synchrotron radiation source 20m
This study addresses X-ray beam stabilization challenges in fourth-generation synchrotron radiation systems by developing an active feedback control system. Replacing passive vibration isolation, the solution integrates high-sensitivity current detection (pA-nA range) for beam positioning with piezoelectric actuators achieving nanometer-scale adjustments. The driver operates at hundreds of mA with mV precision, enabling over 100 Hz regulation frequency. This dual approach ensures precise beam monitoring and control, meeting the stringent stability requirements for advanced synchrotron experiments.
Speaker: Mr Kai Wang (Institute of high energy physics, Chinese Academy of Sciences) -
18:40
High-Speed Data Scouting: Exploring RoCE and 400G Ethernet for CMS Level-1 Trigger Scouting system 20m
The CMS Level-1 Trigger scouting system, planned as part of the HL-LHC upgrade, aims to collect objects reconstructed by the L1 trigger at the LHC bunch crossing rate to perform online physics analyses. As part of this effort, the use of RDMA over Converged Ethernet is being explored to transfer data from the scouting FPGAs to servers, along with the adoption of 400G Ethernet links. A first implementation of RoCEv2 on an AMD Versal adaptive SoC evaluation board is presented. This work aims to extend the physics reach of the CMS experiment allowing for a completely triggerless acquisition system.
Speaker: Matteo Migliorini (CERN) -
18:40
Mass Production of Silicon Strip Tracker End-cap Hybrids and Powerboards for the ATLAS Detector Upgrade: Challenges and Status 20m
For the High-Luminosity Upgrade of the Large Hadron Collider, the ATLAS detector will receive a new silicon strip tracker. The module design utilizes readout hybrid flexes and powerboard flexes glued onto the sensor surface. In total, approximately 13,000 end-cap hybrid readout flexes and 6,000 end-cap powerboards are needed to build both end-caps of the strip detector. This contribution summarizes the latest status of the mass production of hybrid flexes and powerboards performed at the University of Freiburg, focusing especially on the challenges encountered due to quality variations and design decisions.
Speaker: Dennis Sperlich (Albert Ludwigs Universitaet Freiburg (DE)) -
18:40
Multi-Channel Data and Clock Transmission System Based on Free-Space Optical Communication 20m
The Circular Electron-Positron Collider (CEPC), a large-scale international particle physics
facility proposed and led by Chinese scientists, centers around a high-energy circular
accelerator designed to provide electron-positron collision environments. This study
proposes a multi-channel free-space optical (FSO) communication system based on
wavelength division multiplexing (WDM). The performance of the proposed system has been
experimentally validated in a laboratory environment. Experimental results demonstrated a
maximum data transmission rate of 118 Gbps over a distance of 1.5 meters, with multi-
channel clock synchronization achieving sub-nanosecond accuracy and synchronization
precision within 20 picoseconds.Speakers: Jun Hu, Xing Zhou (IHEP) -
18:40
NKF710.24 Gbps serializer test system and qualification results for ALICE ITS3 20m
The ALICE ITS3 project will upgrade the inner silicon tracker layers with wafer-scale (27cm long) MAPS bent around the beampipe. The MAPS transfers its pixel data via 10.24-Gbps differential links driving a 30cm long FPC-cable.
The NKF7 proto-chip serialises a 16-bit static input to 10.24-Gbps output with a measured Bit Error Rate (BER)<10^-15. Irradiation with 32-MeV protons gives σSEU≈10^-12cm2 and NKF7 withstands a TID>10MRad.
Connecting NKF7 16-data inputs to an FPGA allows PRBS generation with (including FPC-cable) open eyes at 5.12-Gbps (BER<10^-15) but closed at 10.24-Gbps (BER>10^-6), possibly originating from bondwire self-induced supply noise and structural DLL bin width deviations.
Speaker: Marcus Johannes Rossewij (Nikhef National institute for subatomic physics (NL)) -
18:40
Optimized Design，Simulation，and testing of Centimeter-Scale AC-LGAD Detectors for Future Colliders 20m
AC-LGAD detectors, recognized as promising candidates for 4D tracking systems, have achieved ~40 ps timing and ~10 µm spatial resolution in IHEP's 50-µm-thick strip sensors. However, centimeter-scale devices face challenges including charge sharing, capacitance, and power consumption. This study presents structural and process optimizations—such as n+ sheet resistance tuning, metal-pitch size, and isolation structures—supported by TCAD simulations. These enhancements improve performance metrics, positioning AC-LGAD as a viable 4D tracking &TOF detector for future colliders. Testing results of IHEP AC-LGAD sensors with strip lengths ranging from 1cm to 4cm will be presented. Simulations results of monolithic LGAD structures are also discussed.
Speaker: Mei Zhao (Chinese Academy of Sciences (CN)) -
18:40
Performance and Quality Control of CMS Phase-2 Pixel Modules 20m
During the High Luminosity LHC, the instantaneous luminosity is expected to reach a peak of $7.5 x 10^{34} cm^{-2}/s$. The current CMS Inner Tracker will have to be entirely replaced to withstand a significantly higher data rate while operating in an harsher radiation environment.
The demanding requirements for the upgrade are met through the use of 65 nm CMOS technology readout chip and a smaller pixel size for the sensor, both integrated into a serial powering chain.
This work presents the Quality Control procedure developments and the results that were used to evaluate the performance of the pixel module prototypes.Speaker: Giorgia Bonomelli (ETH Zurich (CH)) -
18:40
Performance Assessment of bPOL12V Power Modules for the Next LHCb-RICH Front-end Electronics 20m
During the next LHC shutdown the LHCb-RICH subdetectors will undergo a major upgrade and their electronics chain will be redesigned. The new on-detector electronics architecture will employ bPOL12V power modules. This work presents the validation strategy and the test system, which was designed to assess the performance of such modules in various LHCb-RICH configurations. We performed qualitative measurements like: efficiency, transient response, start-up behavior, thermal studies, ripple etc. For our application, we identified working conditions with best compromise between efficiency, thermal dissipation and load. This system will be used to mass-test about 3500 power modules for the next LHCb enhancement.
Speaker: George-Catalin Salavarin (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO)) -
18:40
Petvision planar PET detector development 20m
PET scanners are indispensable imaging tools in modern medicine. In recent years it was shown that a planar configuration, in contrast to the classical cylindrical shape, could become a practical option, while capable to operate in challenging environments and protocols, such as surgery suit, ER, upright imaging, that are not possible using current PET scanners. For such an open tomograph geometry to work, measurement of the positron annihilation into 2 photons must be defined with TOF accuracy better than ~100ps FWHM. We present results of a small prototype system studies, used to investigate optimal configurations scalable to larger detectors.
Speaker: Andrej Seljak (IJS) -
18:40
Process in 6M dual-threshold hybrid pixel detector system design and engineering prototype for HEPS 20m
HEPS-BPIX4 is a dual-threshold hybrid pixel detector with 140μm×140μm pixel size and frame rate up to 1.2kHz . The 6M pixel detector is design for HEPS.
The silicon sensors used for the modules were designed at IHEP.The sensors with a thickness of 450um are fully depleted at about 60 V and normally biased with 100 V.
The 6M pixel array detector consists of 40 modules, with a total pixel number of 5,898,240 and the total active area is 411 mm 294 mm with 100 Hz maximum readout frame rate.Speaker: Li Zhenjie -
18:40
Radiation effects in silicon photonic modulators of the COTTONTAIL chip 20m
We report on results of irradiation experiments with ring modulators and Mach-Zehnder modulators of our current silicon photonic transmitter chip COTTONTAIL. Ex-situ experiments on ring modulators show a significant degradation from a total ionizing dose of more than 3 MGy and a difference in low and high frequency behavior. Forward bias annealing can mostly restore the pre-irradiation characteristics, but can leave a small penalty of up to 3 dB, even after extended annealing. In-situ experiments for continuous measurements while irradiating are currently prepared for ring modulators as well as for Mach-Zehnder modulators.
Speaker: Mr Heinrich Mayer (Karlsruhe Institute of Technology) -
18:40
Readout concept of the future Belle II Vertex Detector 20m
For a proposed upgrade of the Belle II experiment an R&D program has been established to develop a new vertex detector (VTX) made from a single type of depleted active monolithic pixel detector named OBELIX. The chip will provide two LVDS data links with a transmission speed of about 339 MHz. To read out the OBLEIX data it is foreseen to utilize optical links based on the lpGBT chip and the VTRx+ transceiver module, both developed at CERN. We will present a first concept of the VTX readout system and discuss its technical requirements.
Speaker: Christian Irmler (Austrian Academy of Sciences (AT)) -
18:40
Real-time Wiener Deconvolution Algorithm on FPGA for Neutrino Physics 20m
This poster presents an advanced real-time Wiener deconvolution algorithm designed to take advantage of the FPGAs integrated into the JUNO experiment readout boards. Exploiting online reconstruction of the signal generated by PMTs, we expect to enable the detection of low energy depositions, like those generated by transient astrophysical phenomena.
The features of the algorithm are presented, including its capacity to manage high-throughput data streams with minimal latency, its adaptability and resilience in discerning the characteristics of the input data. This study further demonstrates the potential of FPGA-based solutions for neutrino physics.Speaker: Lorenzo Lastrucci (Universita e INFN, Padova (IT)) -
18:40
Receiving and pre-processing the HGCAL front-end trigger primitive data 20m
The first processing stage of the HGCAL Backend trigger primitive generator system for the Phase-2 upgrade of the CMS detector will be implemented using the Serenity ATCA platform. This processing stage is responsible for receiving and pre-processing the trigger data coming from the HGCAL front-end and is composed of several firmware blocks. This contribution will present an overview of the different firmware blocks and discuss the status of their integration and validation on pre-series Serenity boards.
Speaker: Florence Danielle Beaujean Delaune (Centre National de la Recherche Scientifique (FR)) -
18:40
Results from End-of-Substructure card production for the ATLAS ITk Strip upgrade using both the lpGBTv1 and v2 ASIC 20m
The ATLAS Strip Tracker for the HL-LHC uses the End-of-Substructure (EoS) card to connect up to 28 data lines from the silicon sensor modules to the lpGBTs and VL+ ASICs. The EoS provides a 10 Gbit/s optical link to the off-detector systems. We report on the production experience with detailed QC statistics, the issues that were identified with the LpGBTv1 and required a complete reproduction. We report on the first results of the second production run using the fixed lpGBTv2.
Speaker: Peter Goettlicher (Deutsches Elektronen-Synchrotron (DE)) -
18:40
Scalable and Reliable Temperature Monitoring System Based on Raspberry Pi and OPC UA for Detector Control and Safety Systems 20m
This study presents optimizations to the Massive Temperature Readout System (MTRS), a low-cost alternative to traditional PLC-based systems for large-scale temperature monitoring. Our improved MTRS design streamlines hardware by eliminating intermediate microcontrollers and communication modules, reducing complexity and potential failure points. A unified multi-threaded C++ application replaces the original multi-process software, enhancing performance and managing sensor data acquisition and OPC UA server functions within a single process. Furthermore, a novel sensor reading strategy that achieves higher system performance and provides increased channel capacity is implemented. Our optimizations yield a feasible, cost-effective, high-performance MTRS solution for industrial infrastructures.
Speaker: Mr Kadir Yaz (Turkish-German University (TR)) -
18:40
Statistical Modeling and Simulation of Throttling Strategies in the CBM DAQ System 20m
The CBM experiment at FAIR will operate with high-rate, slowly extracted beams from SIS100, reaching interaction rates up to 10 MHz in quasi-continuous spills. To support this, a free-streaming data acquisition architecture is employed. Spill fluctuations under high data load can lead to event fragmentation and data loss. A statistical model of the data flow, incorporating data response of multiple detectors, has been developed. Based on this model, potential throttling strategies for the Timing and Fast Control system are simulated and evaluated to optimize data integrity under bandwidth constraints.
Speaker: Vladimir Sidorenko -
18:40
The challenges of integrating a SoC platform into the CERN accelerator control system for the HL-LHC Beam Position Monitor system 20m
The data acquisition electronics for the new HL-LHC Beam Position Monitor system will be based on a RFSoC, a System-on-Chip with integrated high-speed Analog-to-Digital Converters and Digital-to-Analog Converters.
While modular systems based on industrial computers and FPGA modules are well known and supported across CERN’s accelerators, SoC based systems are still novel, bringing new possible architectures and different integration challenges.
This paper describes the requirements for the integration of the HL-LHC BPM system and it describes a new integration model made possible by the SoC technology, analysing advantages and shortcomings with respect to a traditional modular architecture.Speaker: Irene Degl'Innocenti (CERN) -
18:40
The read-out electronics for the FLASH experiment 20m
We introduce the FLASH experiment and present its electronic read-out system, currently under development. FLASH uses a resonant-cavity in a magnetic field to search for Dark Matter (DM) particles and High-Frequency Gravitational Waves (HFGWs). The cavity is operated at cryogenic temperatures to improve its performance, uses Superconducting Quantum Interference Devices (SQUIDs) as first-stage low-noise amplifiers and FPGA programmable logic coupled with ADCs and DACs to control the SQUIDs and acquire, preprocess and reduce the physics signal into a format suitable for permanent storage and offline analysis.
Speaker: Luigi Calligaris (Universita & INFN Pisa (IT)) -
18:40
The Reliability Evaluation of Back-End Card (BEC) for JUNO Experiment 20m
The Back-End Card (BEC) is a crucial component in the trigger readout chain of the JUNO experiment, serving as the interface between approximately 7,000 Global Control Units (GCUs) and the central trigger system. A total of 163 BECs were installed for deployment in the experiment's underground environment. To support the system's expected long-term operation, we perform a reliability assessment based on historical data, including environmental monitoring (humidity and temperature), production quality control, and operational stability metrics. Statistical modeling methods, such as Weibull analysis, are applied to evaluate potential failure mechanisms and estimate reliability trends.
Speaker: Yifan Yang (Universite Libre de Bruxelles (BE)) -
18:40
The status of the CMS Muon Drift Tubes HL-LHC Upgrade and the Safety System for the new front-end 20m
To sustain the unprecedented radiation and rates of HL-LHC, the readout and trigger electronics for the Drift Tubes (DT) in CMS have been upgraded. The time digitization is implemented on the new OBDT board, and the data are streamed to the new back-end electronics where event building and trigger primitive generation are performed. The development of a new hardware, called MONitor for SAfety (Monsa) system, monitors and enables each single OBDT. In this report, the status of the development and testing of the DT Upgrade electronics, with a focus on the newly introduced safety electronics, is provided.
Speaker: Paolo De Remigis (Universita e INFN Torino (IT)) -
18:40
The Trigger System for the ICARUS Detector at Fermilab 20m
The ICARUS Liquid Argon (LAr) Time Projection Chamber (TPC) detector is taking data on the Booster (BNB) and Main Injector (NuMI) neutrino beam lines at Fermilab with a trigger system based on the scintillation light (detected by PhotoMultiplier Tubes PMT) produced by charged particles on the time of proton beam extraction from the accelerators. The layout consists of National Instruments PXIe instrumentation to evaluate the presence of a certain number of PMT signals over a threshold (Majority level) in coincidence with the beam spill gates. The architecture and the deployment of the trigger system are presented.
Speakers: Simone Copello, Simone Copello -
18:40
Towards a Scalable Data Readout System for Terascale Era Experiments 20m
Future Terascale-era experiments require scalable, high-performance data acquisition (DAQ) systems to handle extreme data rates. We present a DAQ solution based on the Advanced Mezzanine Card (AMC) standard, under development for the Micro-Vertex Detector (MVD) readout chain of the PANDA experiment. This contribution emphasizes the system’s modularity and scalability. A preliminary test card, targeting the power supply architecture and Module Management Controller (MMC), has been assembled and evaluated. We present the test results and recent design improvements of the AMC module, demonstrating progress toward a robust and flexible DAQ platform for the demanding needs of next-generation high-energy physics experiments.
Speaker: Olena Manzhura -
18:40
Towards a SiPM-based Ring Imaging Cherenkov detector at CBM: Design, noise, and radiation hardness challenges. 20m
We present the design, implementation, and characterization of an 8$\times$8 SiPM (AFBR-S4N66P024M) array adapted to the readout electronics of the CBM Ring Imaging Cherenkov detector. The front-end of the array consists of a preamplification stage with low power consumption (12\,mW/channel), high linearity, and low cost. In addition, we evaluated the performance of the SiPMs after neutron irradiation and electrical annealing. The SiPMs were irradiated with different dose from 3$\times 10^8$\,n$_{eq}/$cm$^2$ to 1$\times 10^{11}$\,n$_{eq}/$cm$^2$. We analyze the dark current, dark count rate, crosstalk, afterpulses, and photon resolution.
Speaker: Jesus Pena Rodriguez (Bergische Universität Wuppertal) -
18:40
Validation of the SiPM-on-Tile Readout Chain for the CMS High Granularity Calorimeter 20m
For the upcoming high-luminosity LHC, the endcap calorimeters of the CMS experiment will be replaced by the high-granularity calorimeter (HGCAL), a sampling calorimeter using silicon sensors in the front and plastic scintillators read out by SiPMs in the back. After successfully integrating the SiPM-on-Tile sensors with the Serenity back-end hardware, we have conducted detailed system tests to validate the functionality and performance of the readout chain. In this contribution, we will describe our system validation setup and showcase results from bench-top tests and beam tests.
Speaker: Fabian Hummer (Karlsruhe Institute of Technology)
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17:35
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Committee meeting
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Logic AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES)), Prof. Johan Alme (University of Bergen (NO))-
09:00
A Versatile Readout System for Front-End ASICs with HLS-based Hardware-Accelerated Processing Capabilities 16m
This paper presents a versatile readout system for particle detector front-end ASICs based on the AMD Zynq Ultrascale+ System-on-Chips. The system is suitable for both extensive laboratory characterization and for data acquisition at testbeam facilities. Its software-level scripting of the test procedure reduces the firmware development effort, maximizing the system reusability among different DUTs. At the same time, the integration with High-Level Synthesis flows allow the deployment of demanding pipelined and parallel processing algorithms in hardware, offloading the ARM processor. In the presentation the architecture of the system is presented along with the experimental results obtained in different use cases.
Speaker: Valerio Pagliarino (INFN Torino and Politecnico di Torino) -
09:20
A Latency-Constrained, Gated Recurrent Unit (GRU) Implementation in the Versal AI Engine 16m
This work explores the use of the AMD Xilinx Versal Adaptable Intelligent Engine (AIE) to accelerate Gated Recurrent Unit (GRU) inference for latency-Constrained applications. We present a custom workload distribution framework across the AIE's vector processors and propose a hybrid AIE–Programmable Logic (PL) design to optimize computational efficiency. Benchmarking against existing FPGA GRU implementations using a top quark jet tagging dataset demonstrates promising latency results. Our approach highlights the potential of deploying adaptable neural networks in real-time environments such as online preprocessing in the readout chain of a physics experiment, offering a flexible alternative to traditional fixed-function algorithms.
Speaker: Michail Sapkas (Universita e INFN, Padova (IT))
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09:00
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Trigger MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Conveners: Ioannis Kopsalis (National Technical Univ. of Athens (GR)), Mr Ioannis Kopsalis (University of Birmingham (GB)), Salvatore Danzeca (CERN)-
09:00
Development and demonstration of a CMS Phase-2 Level-1 trigger Data Scouting baseline system for HL-LHC 16m
The CMS Phase-2 upgrade for the High-Luminosity LHC introduces the Level-1 Data Scouting (L1DS), a novel data acquisition system that captures and processes Level-1 (L1) trigger information at the full 40 MHz collision rate. The L1DS bypasses the L1 selection to enable searches for signatures previously limited by L1 constraints. This contribution presents the development of a Phase-2 L1DS demonstrator system. A DAQ-800 custom FPGA board performs the L1 data readout and zero-suppression. Pre-processed data is transmitted to a server cluster for event building and online analysis. Validation is done on simulated collisions and running rare Standard Model decay analyses.
Speaker: Mr Rocco Ardino (CERN) -
09:20
Finalization of the Sector Logic ATCA blade design for the ATLAS Level-0 muon trigger at HL-LHC 16m
The TDAQ of the ATLAS experiment will be upgraded in alignment with the High-Luminosity LHC project so that the trigger rate increases from 100 kHz to 1 MHz. As the hardware muon trigger of TGC (RPC) for the endcap (barrel), we developed a Sector Logic ATCA blade consisting of a large-scale FPGA, AMD Virtex UltraScale+, and 10 Gbps optical transceivers. In two prototyping phases, we evaluated the prototype boards, especially regarding the power management, the fixed clock phase alignment, and the inter-system test. Consequently, we established the final design for mass production in 2027. These results will be presented.
Speaker: Shota Izumiyama (Nagoya University (JP))
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Break 30m
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Logic AQUILLES, Aquila
AQUILLES, Aquila
Conveners: Andrea Boccardi (CERN), Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))-
10:10
Operations and optimizations of the FPGA-based real-time cluster-finder architecture in the LHCb silicon pixel detector 16m
The LHCb-UpgradeI experiment has adopted a heterogeneous computing-based trigger system that relies on the reconstruction of all collision events, occurring at 30MHz. In this context, a two-dimensional FPGA-based cluster-finding architecture has been developed to reconstruct in real time hit positions in the vertex pixel detector, capable of processing $\sim10^{11}$ hits/second, and freeing computing resources of the high-level-trigger.
We report on developments and design optimizations of the cluster-finder firmware, based on the operational experience acquired in 2024 while running at the LHCb-UpgradeI design luminosity, as well as new firmware implementations to support the high-occupancy conditions unique to the LHC Heavy-Ion program.Speakers: Daniele Passaro (SNS & INFN Pisa (IT)), Federico Lazzari (Universita di Pisa & INFN Pisa (IT)) -
10:30
Hardware-Accelerated GNN Hit Filtering for the Belle II Level-1 Trigger 16m
We present a real-time hit filtering system based on Graph Neural Networks (GNNs), implemented on FPGAs for the Level-1 trigger of Belle II. The system processes raw data from 14,336 sense wires with a sustained throughput of 32MHz and sub-microsecond latency. It combines GNN inference with static graph-building logic in a latency- and resource-optimized FPGA pipeline. This work demonstrates a scalable, low-latency architecture for detector-level background suppression, enabling efficient real-time data reduction in high-rate collider environments.
Speaker: Greta Sophie Heine
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10:10
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Trigger MEGAS ALEXANDROS, Aquila
MEGAS ALEXANDROS, Aquila
Conveners: Ioannis Kopsalis (National Technical Univ. of Athens (GR)), Mr Ioannis Kopsalis (University of Birmingham (GB)), Prof. Johan Alme (University of Bergen (NO))-
10:10
Standalone Timing Distribution and Event Capture Firmware for Back-End Electronics Test Stands 16m
Timing and control firmware was developed to operate a vertical slice of the CMS high-granularity calorimeter front-end and back-end systems at beam tests, in the absence of a full-fledged system. It provides various trigger sources (software, regular, random, external), throttling mechanisms and a programmable sequencer of fast commands. A data capture block for local readout of the outgoing event data through an IPBus interface complements this development. Such integration facilitates the development of standalone BE systems without specialized timing/trigger distribution or DAQ hardware. Modular design of the firmware and software enables easier adaptation for other detector subsystems.
Speaker: Raghunandan Shukla (Imperial College (GB)) -
10:30
The ATLAS Tile Calorimeter Trigger and Data Acquisition Interface: Development, Integration and Validation 16m
Future High Luminosity LHC runs introduce more simultaneous proton-proton collisions for the LHC experiments. The ATLAS Tile Calorimeter (TileCal) plans a replacement of the on- and off-detector electronics to meet the requirements for faster data processing. New off-detector electronics provide high-bandwidth data to the upgraded Trigger and Data Acquisition (TDAQ) system. The Tile Calorimeter Trigger and Data Acquisition Interface (TDAQi) as part of the TileCal PreProcessor serves as the connection between the calorimeter electronics and various subsystems of the trigger and read-out system. The TDAQi processes individual cell information into multiple trigger primitives of different granularity under strict latency requirements.
Speaker: Thomas Junkermann (Heidelberg University (DE))
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10:10
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Break 1h 20m
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Tutorials
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