Speaker
Description
The LiTE-DTU is an ASIC designed to digitize and transmit scintillation signals from the CMS Electromagnetic Calorimeter (ECAL) at HL-LHC. The chip was produced in TSMC 65 nm technology. The development process of the chip was not without hurdles, going through three prototype cycles and two engineering runs. Functionality and performance has been assessed in four test-beam campaigns. 96k chips have been packaged and tested in industry. We share our experience with the LiTE-DTU development, attempting to help saving time and effort in future similar efforts. Quantitative results from performance measurements and test statistics will complete this contribution.
Summary (500 words)
The LiTE-DTU (Lisbon Torino ECAL Data Transmission unit) project was a success, in that the chip meets performance specifications, accumulated a delay compatible with HL-LHC schedule and ran only slightly overbudget, despite its development during an unfavourable world economy situation. The ASIC is equipped with two 12-bit ADCs running at 160 MHz and data transmission unit that features lossless compression. Two irradiations with heavy ions helped to measure SEU cross sections as a function of LET. An incremental X-ray exposure proved TID resistance above 50 kGy. Four test beam campaigns, of which two with the complete readout chain, measured the performances in realistic conditions and allow the team to deploy the upgraded electronics with confidence. Test beam analysis showed that the goal of measuring photons from Higgs decay with a time resolution below 30 ps is met. The design and production cycle encountered a few unexpected difficulties. In the very first prototype, a design error with the distribution of the I2C clock resulted in communication problems with most of the about 40 samples that were manufactured. A first engineering run was executed using the wrong process flavor, which resulted in power consumption being higher by 20% with respect to expectations and previous prototypes. The problem was identified only several months past reception, after in-depth investigations including LIT tomography. On the positive side, design reviews between prototypes and vertical integration helped identifying details and optimize performance. Interaction with the test company was not trivial. In particular, it is difficult to draw the line between what is provided by the industry and what is the responsibility of the designers. Also, setting test acceptance limits is a matter of balance. We offer the details of the test setup and mass production and test experience. In this contribution we will briefly describe the chip and its goals, the development cycle, the design of the mass test. We will show updated performance measurements from both lab bench and large-scale vertical integration with electron beams. We will report on test statistics from the full production testing. Most importantly, we will focus on the lessons learned, in the hope to save time and effort for future projects. By the time of TWEPP 2025, we hope to meet the LiTE-DTU endgame, with 75000 tested chips and several thousands of them mounted on the production Very Front End boards.
