Speaker
Description
Superconducting nanowire single-photon detectors (SNSPDs) are promising candidates for novel particle detectors offering picosecond timing resolution, but are difficult to scale to large arrays. We present a 32-channel cryo-CMOS ASIC, fabricated in a 22nm FDSOI process, designed for tight integration with SNSPDs and operation at 4K. The ASIC targets 8.0ps RMS timing accuracy across 32 channels and includes on-chip bias generation, low-noise amplifiers, high-resolution time-to-digital converters (TDCs), and serializers for interfacing with room-temperature electronics. Measuring 4.0mm × 1.0mm, the ASIC addresses the challenge of scalable SNSPD readout. Initial results using a Caribou-based DAQ system will be presented.
Summary (500 words)
Superconducting nanowire single-photon detectors (SNSPDs) are leading technologies for time-resolved single-photon detection, offering state-of-the-art performance in terms of detection efficiency, timing jitter, and dark count rates. These detectors are increasingly used across a range of applications, including quantum information systems and particle detection. While efforts to scale SNSPDs to large arrays have made progress, current solutions such as thermally coupled row-column readout architectures face limitations in occupancy and readout rates.
To address these challenges, this work presents a 32-channel cryogenic CMOS ASIC designed for modular, scalable SNSPD array readout with picosecond timing resolution. Designed for operation at 4 K, the ASIC provides integrated biasing and event time-tagging functionality, enabling precise control and readout of superconducting devices such as SNSPDs and nTrons.
The ASIC architecture includes 32 analog readout channels, each with a programmable current source for biasing (1.0 μA to 100 μA), a programmable impedance (20 Ω to 1.0 kΩ) for passive quenching, a low-noise amplifier, and a dedicated fine time-to-digital converter (TDC) for event timing. Additionally, five analog bias channels provide further flexibility for device biasing and control, though these channels omit amplifiers and TDCs.
The ASIC’s timing system is a distributed architecture combining fine TDCs local to each channel and a shared coarse TDC. The TDCs measure the timing of detected events by comparing the event signal to a reference clock generated by an on-chip low-jitter PLL. Fine TDCs use Vernier delay lines to achieve high resolution, and timing information is formed by combining fine and coarse TDC measurements.
The digital readout subsystem handles timestamp aggregation and serialization. It supports both dynamic and fixed priority modes for timestamp transmission and includes features for diagnostics and configuration reporting. Four high-speed LVDS-compatible output drivers serialize the data at 1.0 GHz for transmission to room-temperature electronics such as FPGAs.
Fabricated in a 22 nm FD-SOI CMOS process, the ASIC occupies a 4.0 mm × 1.0 mm footprint and operates at 4 K. The design leverages cryogenic device models derived from experimental measurements to ensure reliable performance at low temperatures. The system is targeted to achieve 8.0 ps root-mean-square timing accuracy with a total power consumption of 114 mW. Testing of the fabricated ASIC is underway, and results will be presented at the conference.