Speaker
Description
The CMS High Granularity Calorimeter (HGCAL), developed for the HL-LHC, uses custom ASICs—HGCROC3 and H2GCROC3—to read out silicon sensors and SiPM-on-tile modules. These chips provide precise charge and timing measurements, digital processing for triggering, and are designed to operate in harsh radiation conditions. Version 3 of the chips implements all final features, with sub-versions A–E addressing bugs and improving radiation tolerance. Extensive testing has been performed in lab and beam environments. The presentation covers chip design, performance, SEE-related issues, and the automated production testing.
Summary (500 words)
The High Granularity Calorimeter (HGCAL), currently under production by the CMS collaboration for the HL-LHC upgrade, will replace the existing endcap calorimeters with a design offering unprecedented transverse and longitudinal segmentation for both readout and triggering.
Its electromagnetic section and part of the hadronic section are based on hexagonal silicon sensors, while the remaining hadronic section, located in a lower radiation region, uses scintillator tiles read out by SiPMs.
Two dedicated front-end ASICs have been developed: HGCROC3 for silicon sensors and H2GCROC3 for the SiPM-on-tile readout. Both chips measure and digitize the charge collected from the silicon pads or generated by the SiPMs, respectively. They also provide high-precision time-of-arrival (ToA) measurements and transmit digitized data to the back-end electronics. Additionally, they compute, at every bunch crossing, digital sums of neighbouring channels. These sums are compressed and sent to the concentrator ASICs via 1.28 Gbps serial links to build trigger primitives.
The design requirements for the front-end electronics are extremely demanding: a dynamic range equivalent to over 16 bits, low noise, precise timing (better than 25 ps) to mitigate pile-up under high luminosity, and low power consumption (less than 15 mW/channel). The ASICs must also operate in a harsh radiation environment, with expected exposures up to 200 Mrad and 1×10¹⁶ neq/cm² by end-of-life.
Beyond analog performance, the chips incorporate significant digital processing capabilities to manage both Trigger and Data paths. A two-stage memory buffering system is implemented using DRAMs to handle the 12.5 µs Level-1 (L1) trigger latency and the readout buffer, with memory depths of 512 and 32, respectively. Radiation hardening against Single Event Effects (SEE) is achieved through triple modular redundancy (TMR) of all control logic and configuration parameters.
Each ASIC has 72 channels and six 1.28 Gbps outputs (four for trigger, two for DAQ).
While versions 1 and 2 were submitted without the full functionality, version 3 fully implements the features specified in the Technical Design Report (TDR) and meets the target performance.
Five sub-versions of version 3 (A to E) were developed to address performance optimization, bug fixes, and improvements in radiation tolerance, particularly with respect to TID and SEE sensitivity.
This presentation will detail the architecture, performance, and validation of both ASICs.
Extensive validation has been conducted in laboratory conditions, at cold temperatures, under TID stress, and in 70 MeV proton beams. The chips have also been tested in beam campaigns using fully assembled modules with both sensor technologies.
A special focus will be given to observed SEE-induced limitations and the corrective actions implemented across sub-versions. The talk will conclude with a presentation of the automated production testing setup using robotic systems and the current production strategy.