Speaker
Description
The ALICE 3 Time of Flight detector requires a time resolution below 20 ps to allow for electron and charged hadron identification from 15 MeV/$c$ (forward e/$\pi$ separation) to 4 GeV/$c$ (p/K separation).
The expected event rate, of about 280 kHz/cm$^2$, makes monolithic CMOS sensors very attractive.
However, their time resolution is still far from the experiment needs.
A solution is to incorporate a moderate gain (10-30) in the active region. For this, a dedicated R&D in a standard 110nm node is underway.
In this presentation, the device concept is discussed, and the experimental results obtained so far are presented.
Summary (500 words)
The Time of Flight system of the ALICE 3 experiment requires a time resolution of 20 ps. Depending on the final detector layout, a total surface of 45 m^2 should be instrumented. The pixel pitch must be below 1 mm, while an event rate of 280 kHz/cm^2 is expected.
Due to their simplicity and cost-effectiveness, monolithic sensors would be ideally suited, but their time resolution must be improved. Indeed, several R&D efforts are ongoing in different institutes. A possible approach is to extend the standard Low Gain Avalanche Diode (LGAD) concept to a CMOS technology by adding a gain layer underneath the collection electrode. The advantage of this solution is that it is easily compatible with any CMOS Imaging Sensor process (CIS) with the addition of only one extra mask to the fabrication process. In this case, the collection electrode must be kept at a moderate voltage (30-60 V), imposing an AC coupling between the sensor and front-end electronics. A dedicated R&D is underway at INFN to investigate this concept. The project is carried out in synergy between ALICE and the INFN ARCADIA collaboration which explores the design of CMOS Monolithic Active Pixel Sensors (MAPS) using the 110nm technology of LFoundry.
The CMOS LGAD were implemented in the third ARCADIA engineering run. The sensor and the electronics are hosted in the same n-type, epitaxial layer which can be fully depleted [Figure 1], thus establishing drift as the main charge collection mechanism. A deep p-well ring around the collection electrode provides the space for the very front-end electronics based on a cascoded common source stage implemented with 1.2 V transistors. This stage is then followed by an analogue buffer designed with 3.3 V transistors to drive the output analogue pads [Figure 2]. The prototype is composed of 8 matrices of 64 pixels and 128 analogue outputs. The read-out board was designed with 4 analogue outputs as it is typically tested with a 4 GHz, 20 Gs/s oscilloscope.
A time resolution of 154 ps [Figure 3] and a sensor gain of around 3 were measured with the first prototype. These tests allowed us to understand the best sensor optimization strategy. A new production run was submitted to the foundry with the same set of masks used for the prototype but with different doping of the gain layer.
The new structures were also tested in a test beam and a gain of around 10 and a time resolution of around 90 ps were measured [Figure 4]. In parallel to the beam tests at CERN, the new prototype was characterised at DESY in combination with a tracker to study in detail the time resolution as a function of the particle impinging position in the pixel.
These results were obtained on wafers with 50 um active thickness.
In the presentation, the sensor design concept and the measurements performed so far will be discussed along with the challenges addressed in the course of the project and the strategies to reach the 20 ps goal.
