Speaker
Description
The FastRICH ASIC provides high-precision, triggerless readout for Upgrade-Ib of the LHCb RICH detectors. Demands of continuous data acquisition and varying hit rates across the detector impose unique challenges on the ASIC's design and verification. This work presents the verification strategy for FastRICH, focusing on functional correctness, timing performance, and operational robustness. The methodology includes simulations across occupancy scenarios, validation of timing precision, and stress testing under pile-up and high-rate conditions. Results demonstrate that FastRICH meets its performance requirements over the full range of expected occupancies. Key design and verification challenges are discussed, along with lessons learned for future developments.
Summary (500 words)
The FastRICH ASIC has been developed as part of the Upgrade Ib program for the LHCb RICH detector to enable fast, precise, and triggerless readout of single-photon signals across a wide range of expected occupancies. The design integrates 16 independent input channels, each equipped with a Time-to-Digital Converter (TDC) capable of achieving a nominal resolution of 25 ps.
A key challenge in the design and verification of FastRICH lies in maintaining high timing precision and low deadtime performance across a broad dynamic range of occupancies. Depending on the location within the RICH detector, average hit occupancies can vary significantly, ranging from 0.1 channels hit per Bunch-Crossing (BX) to six channels hit per BX. The ASIC must operate reliably across this spectrum, delivering accurate timestamping and data integrity under all conditions.
To ensure that the FastRICH ASIC meets its performance requirements, a comprehensive coverage-driven verification strategy was employed, using Universal Verification Methodology (UVM). This approach integrated RTL simulations, gate-level simulations, performance characterization, and Single Event Effects (SEE) robustness checks, all within a modular and reusable UVM testbench. Special attention was given to validating performance at both ends of the occupancy spectrum. In low-occupancy conditions, the system was required to operate without introducing spurious noise, while in high-density bursts of hits, the verification needed to ensure that deadtime was minimized and data loss was prevented.
The verification methodology was built around several core principles. First, self-checking and automated test frameworks were employed to verify that rare edge cases, such as simultaneous multi-hit events and near-saturation conditions, were thoroughly covered and validated. Precision timing validation was critical to ensure that the TDCs maintained their linearity and resolution of 25 ps across all channels. Occupancy stress testing was another major component, where synthetic hit patterns were generated to simulate both low and high-occupancy scenarios. This allowed the evaluation of internal buffering, deadtime behavior, and multi-hit resolution capabilities. Additionally, jitter robustness was assessed by introducing clock variations to test the resilience of time measurements under less-than-ideal conditions.
The verification process involved simulating and analyzing performance metrics such as TDC linearity, deadtime, readout latency, and occupancy-dependent throughput. The results confirmed that the FastRICH ASIC meets all performance targets, with timing resolution consistently within specification across occupancy conditions and minimal deadtime, even under high-rate scenarios.
Verification of FastRICH ASIC provided important insights into subtle aspects of triggerless high-precision timing ASIC operation. Without a hardware trigger to limit or synchronize data flow, particular care had to be taken to verify timestamping consistency, buffering strategies, and hit arbitration mechanisms. The wide dynamic range of hit rates and precise timing required flexible verification methodologies, and the lessons learned in this process are likely to remain relevant for future triggerless, high-precision readout ASICs in particle physics and beyond.
