Speaker
Description
The High Granularity Timing Detector (HGTD) for the ATLAS experiment, within the HL-LHC upgrade, uses Low Gain Avalanche Diode (LGAD) sensors for high-precision timing measurements.
AltirocA is the pre-production 225-channel readout ASIC, providing both luminosity and time-of-arrival measurements. The full system targets a resolution of 30 ps per hit initially and 70 ps after full irradiation.
Production of 25,000 AltirocA ASICs will begin this summer. Extensive testing was performed at various stages, including standalone, hybrid, and module setups. Tests were conducted under irradiation, in test-beams, and with a probe station at wafer level.
This contribution presents performance and difficulties encountered.
Summary (500 words)
The High-Luminosity phase of the LHC (HL-LHC), with instantaneous luminosity reaching up to L ≃ 7.5 × 10³⁴ cm⁻² s⁻¹, will produce an average of 200 interactions per bunch crossing. To mitigate the resulting pile-up effects, the High Granularity Timing Detector (HGTD) will be installed in the forward region (pseudo-rapidity range 2.4–4.0). This detector will provide high-precision timing measurements, enabling the separation of spatially close but temporally distinct collisions.
The HGTD consists of two double-sided layers of Low Gain Avalanche Diode (LGAD) sensors, designed to deliver precise timing for minimum ionizing particles. The target performance is a time resolution better than 70 ps per hit, corresponding to 50 ps per track at the end of the detector’s lifetime. This precision is critical for accurately associating particles with their primary interaction vertices.
ALTIROCA is the pre-production version of the HGTD readout ASIC. The active detector area is covered by modules, each consisting of two ALTIROC ASICs bump-bonded to two 15 × 15 pixel LGAD sensor matrices. Each pixel measures 1.3 mm × 1.3 mm and has a capacitance of 4 pF—relatively high for the required low detection threshold of 2 fC. The ASIC is designed to withstand harsh radiation environments, tolerating up to 2 MGy of Total Ionizing Dose (TID) and a fluence of 2.5 × 10¹⁵ neq/cm².
Each ASIC channel integrates a 1 GHz bandwidth preamplifier, a fast leading-edge discriminator, and two Time-to-Digital Converters (TDCs) for measuring both Time-of-Arrival and Time-Over-Threshold. It also includes a 38.4 µs deep memory buffer with pixel-level zero suppression to optimize data throughput.
Beyond timing, the ASIC provides luminosity monitoring by counting hits per bunch crossing. Timing data is transmitted at up to 1.28 Gb/s, while luminosity data is sent at 640 Mb/s. The ASIC employs a Digital-On-Top architecture with Triple Modular Redundancy (TMR) to ensure robustness against Single Event Effects (SEE), while the front-end analog part is implemented with an Analog-On-Top floorplan.
Testbench measurements demonstrate that the ASIC and hybrid detect charges as low as 4 fC with 95% efficiency. The measured time jitter is below 25 ps for a 10 fC input and 65 ps for 4 fC, satisfying the stringent HGTD requirements. These results are confirmed for the full modules that will equip the detector.
SEE and latch-up tests show good robustness. Under TID stress, performance remains stable up to 2 MGy, though an unexpected dependence of TDC bin widths on dose rate was observed. External mitigation techniques reduce these variations by a factor of three, bringing them within specification, though the root cause remains unexplained.
Several test beam campaigns using non-irradiated and irradiated hybrids as well as full modules achieved time resolutions between 45 and 55 ps.
This talk will present key results, the challenges encountered, and the lessons learned during the design and characterization phases.