Speaker
Description
This work presents the results of proof-of-concept ASIC implementing a novel TDC based on Time-to-Amplitude Converter (TAC) architecture demonstrating a best-case precision of 0.83 ps in a compact area (~0.021 mm²) and with low power (~2.6 mW per channel) making it suitable for high-density integration, typical of HEP applications.
It performs a time interval measurement between events by sampling a periodic signal, obtained by interpolating the nodes of a free running oscillator.
It demonstrates a worst-case precision of 1 ps for time intervals up to 3 ns and 3.68 ps up to 25 ns, with 1.79 LSB peak-to-peak INL.
Summary (500 words)
Time-to-Digital Converters (TDCs) with picosecond-level precision and high-rate capabilities, up to tens of MHz per channel, are increasingly relevant for applications such as Light Detection And Ranging (LiDAR), medical imaging, and High Energy Physics (HEP), where low power, compact area and high scalability are key requirements to enable the integration of hundreds of channels.
This work presents a novel TDC architecture, based on a Time-to-Analog Converter (TAC), which measures the time interval between events by sampling a periodic signal for fine time measurement with 0.95 ps resolution. Counting the periodic signal cycles between the events allows a coarse measurement that extends the range up to 25 ns. The architecture implements the patent EP3591477A.
A proof-of concept ASIC has been implemented and tested in 130 nm CMOS technology demonstrating a best-case precision of 0.83 ps. The worst-case precision is 1 ps for time intervals up to 3 ns and 3.68 ps up to 25 ns. The chip is approximately 1 mm², with an active area of 0.021 mm² and power consumption of ~2.6 mW per channel and ~1 mW dynamic power. The maximum peak-to-peak INL is 1.79 LSB.
While several TDCs architectures have been proposed, they often struggle to combine picosecond precision, low power, and compact area when scaled to many channels. The proposed architecture addresses this challenge by preserving performance across multiple channels with a minimal area and power budget.
The ASIC uses an 11-stage single-ended CMOS free-running oscillator and a resistive interpolator as a reference signal generator, providing two periodic pseudo sinusoidal signals, both with the oscillator period T, shifted by ~T/4 with respect to each other.
A start-stop channel pair samples the reference signals using Sample-and-Hold circuits. The samples are used to reconstruct fine time information after calibration within one oscillation period. The sampled voltages are buffered via rail-to-rail buffers and digitized by external 12-bit ADCs. Coarse timing is performed in parallel using a fast counter based on a Linear Feedback Shift Register (LFSR). Data is serialized and sent to a custom DAQ.
The combination of the oscillator, counter and TAC architecture enables a compact, low-power and technology-node-independent TDC. The free running oscillator provides benefits like low power, small area, and simple design, but requires frequency calibration.
One of the challenges is the offline reconstruction of time intervals from the digitized sampled signals. During calibration phase, the samples are mapped to phase angles using the arctan2 function, covering the full range [0,2π]. These angles are grouped into N bins using equal-time binning criterion ensuring a linear time mapping. During the time interval measurement, the digitized samples are converted to phase angles and assigned to the corresponding calibration-derived bins. The time is finally reconstructed as the bin index multiplied by the resolution, defined as T/N.
The advantages of the proposed architecture with respect to other approaches in literature will be presented, together with an in-depth analysis of the jitter performance and the results of the proof-of-concept.
