Speaker
Description
This work presents the design challenges and characterization results of the novel 100µPET detector ASIC. The 100µPET project proposes an innovative scanner for small animals made of a stack of high-granularity, thin, full-reticle MAPS (30.2 x 22.8 mm²), and promises unprecedented volumetric resolution of 0.022 mm³. The chip features ~25k hexagonal pixels with 93 µm side in 130 nm SiGe BiCMOS. The in-pixel frontend achieves an ENC < 200 electrons, with 200-ps-level jitter and power consumption below 100 $\text{mW/cm}^2$. The ASIC includes 150 ps resolution TDCs, a pipelined 50 MHz projection-based readout, and handshaking protocol for daisy-chained, single line readout.
Summary (500 words)
The 100µPET project is developing a prototype of a small-animal Positron Emission Tomography (PET) scanner with ultra-high, unprecedented spatial resolution to specifically perform molecular imaging of atherosclerotic plaques. For this system, a 60-layer stack of interleaved, high-granularity, tracking monolithic sensor and 50 µm-thin tungsten layers replaces the scintillating crystals of conventional PET systems. The novel architecture exploits the thin, segmented ASIC in each layer to detect the products of the 2 back-to-back photons conversions in the tungsten, improving volumetric resolution to 0.022 mm³, one order of magnitude better than state-of-the-art scanner.
The full-reticle ASIC (~ 30.2 x 22.8 mm²) was manufactured in IHP 130 nm SiGe BiCMOS technology. It features a monolithic silicon pixel sensor with 93 µm side hexagonal pixels arranged in a 132 x 192 matrix. Each pixel acts as a 3D independent detection channel. The high-resistivity (4 kΩ·cm) wafer used for the design was thinned to 270 µm and it is fully depleted to achieve the target sensitivity and charge-collection time.
The in-pixel circuitry achieves an ENC < 200 electrons and an operating threshold of 3000 electrons, but the stringent power budget of 100 $\text{mW/cm}^2$ limits the timing resolution to 200 ps. A pixel-level 3-bit threshold tuning DAC mitigates the mismatch, enhancing uniformity across the whole matrix and limiting the operating threshold for enhanced detection efficiency.
The matrix is divided into 16 super-columns of 132 x 12 pixels, each representing an independent data processing unit to support parallelized readout. This unit includes masking and test-pulsing logic, distributed in the pixel matrix and creating a non-sensitive column of 2.1 cm x 50 µm, 1/13 of the active area.
The ASIC is designed to detect single cluster events of maximum 5x5, as expected from Monte Carlo simulations, with a modular event-driven readout architecture. The discriminated output from each hit pixel is sent asynchronously to the periphery logic at the bottom of the ASIC through a 51-bit projection system per super-column, to compress the interconnect design while limiting the risk of ghost hits. These lines were carefully balanced by hand to limit the skew along the super-column, ensuring a good detection efficiency for coincidence hits in the scanner. In addition, a TDC with 150 ps resolution recovers for each projection bus the Time-of-Arrival of the fastest channel with sub-clock period precision, as well as the Time-over-Threshold to perform time-walk correction.
The ASIC’s periphery logic handles the configuration phase and the aggregation of the super-columns’ bits with the timing data on a single 50 MHz serial output line, based on fixed, non-absolute priority encoding. To limit pile-up and data loss at the expected rate of 6 $\text{kHz/cm}^2$, a modular tree-like architecture with a 3-level buffer pipeline was implemented for the periphery readout logic. The periphery also manages a handshaking protocol to connect 4 chips in daisy-chain on the same data line, to reduce the number of output connections per module.
We present the design and the characterization results of the first assembled, functioning prototypes, currently undergoing extensive functional and integration tests.