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Description
The CALOROC1B ASIC has been designed to read out the SiPMs for the ePIC detector at the EIC collider. Each of its 36 channels is composed of a high-gain preamplifier, two low-power preamplifiers, a dynamic gain switching mechanism, a shaper, and two ADCs to read the energy, with a discriminator connected to a TDC for time-of-arrival measurements. This work presents the ASIC architecture and its simulation results. The ASIC has been designed to read large SiPMs (up to 10nF), be resilient to radiation, and have a large dynamic range (up to 140k measured as Qmax/Noise) while keeping a good resolution.
Summary (500 words)
CALOROC1B is an ASIC designed to read out large SiPMs for the ePIC detector at the EIC. This chip is based on the developments realized for the HKROC and H2GCROC (CMS) chips. The first prototype of CALOROC1B was submitted in 130 nm node and lab tests are planned for September 2025.
CALOROC1B is a complex system-on-chip with analog and digital processing. It embeds 36 independent channels working in a trigger-less fashion (streaming readout) and dissipates 10mW per channel.
To achieve a large dynamic range, each channel has a dynamic gain switching mechanism to dynamically connect the different preamplifiers to the ADC depending on the input charge.
The ASIC’s preamplifiers are AC coupled to the channel input, allowing this circuit to read large SiPMs. Using a 6x6mm2 SiPM, the circuit can read up to 1.55nC while keeping a RMS noise of 11fC. Using a larger SiPM can increase the maximum measurable charge but it also increases the RMS noise keeping the dynamic range (Qmax/Noise) constant.
CALOROC1B trigger-less mechanism (streaming readout) is based on an internal trigger generated according to the input signal level. Each channel of the chip is made of a low-noise input preamplifier and two low power preamplifiers. An analog multiplexer dynamically connects the three preamplifiers through a shaper to a 10-bit 40 MHz successive approximation Analog-to-Digital Converter (SAR ADC from AGH Krakow).
A discriminator is connected to a 10-bit Time-to-Digital Converter (TDC from CEA IRFU group) for time measurement with 25 ps accuracy.
The TDC is only activated when the input signal is higher than a defined threshold. When triggered, it opens an acquisition window where all input signals are digitized, stored and automatically read out. The TOA is directly given by the TDC. For the charge, the shaper output is continuously sampled by the ADC at 40 MHz. Only during the acquisition window, the digitized samples are stored inside a memory.
The ASIC intends to be a versatile readout chip and it has many configuration registers to tune its behavior. The parameters can be loaded and verified through a standard I2C protocol: all the internal parameters are triplicated for redundancy.
Many clocks are required internally for sub-modules (I2C, ADC, TDC): they are all derived from one incoming fast clock (around 320 MHz) thanks to an internal PLL. An incoming bit-stream is attached to this clock and can be used to send fast commands to control internal digital processing of the ASIC: link synchronization, external triggering or calibration. The digital processing of the circuit is handled at 40 MHz: to limit the coupling of the digital activity on the analog part, a phase-shifted 40 MHz is created internally and sent to all the digitizers (ADC and TDC). By default, the chip works in a trigger-less and autonomous mode. After being zero-suppressed, the relevant data (charge and time) are stored into local memories and then readout through two high speed differential links working at 1.28 Gbps.