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Description
This work evaluates how stage count, gate length, and load capacitance tuning affect radiation tolerance in CMOS inverter based ring oscillators using a newly developed Dynamic Voltage-Dependent (DVD) Single-Event Transient (SET) model validated in a 65\,nm CMOS technology. The model captures n- and p-type Single Event Phase Transients (SEPTs). Simulations are performed under worst-case conditions (1.15,V supply, 75$^\circ$C, slow-slow corner) to evaluate maximum timing effects. While stage count tuning preserves SEPT sensitivity, length and capacitance scaling degrade timing error robustness. This study offers guidance on selecting frequency control techniques that minimize radiation-induced timing errors in ring oscillators.
Summary (500 words)
This work investigates how three frequency-tuning techniques: (i) inverter stage count adjustment, (ii) gate length scaling, and (iii) output capacitance variation affect both performance and radiation-induced sensitivity in CMOS ring oscillators. Each offers frequency control flexibility, yielding different SEPT responses. This study aims to identify which tuning approach provides the best trade-off between frequency control and radiation tolerance.
Simulations measured the peak-to-peak timing error across a full injection sweep over one oscillation period. Two types of injections were performed: (i) small-signal Periodic Steady State (PSS) impulse injections, and (ii) realistic n- and p-type transient SET injections using a VerilogA model. All tests were conducted under worst-case conditions (1.15 V supply, 75 °C temperature, and SS process corner), with each node including 0.2 fF interconnect capacitance and a fanout of one. The baseline circuit is a five-stage ring oscillator (W/L = 1000 nm/100 nm NMOS, 2500 nm/100 nm PMOS), operating at 4.88 GHz. Tuning techniques allow this frequency to be scaled down to 2.2 GHz.
To quantify time error sensitivity, we use the time error per unit injected charge, expressed in seconds per Coulomb (s/C). The oscillator's time error is proportional to Δt = Q_inject / (C_node × SR), where Q_inject is the injected charge, C_node the node capacitance, and SR the slewrate.
In stage count scaling (5 to 11 stages), all inverters are uniformly sized and loaded, resulting in a constant slew rate across configurations. As a result, the time error sensitivity, whether derived from the PSS analysis or transient simulations, remains effectively unchanged. This shows that SEPT does not vary for different stages, making it a safe design choice.
In gate length scaling (100 nm to 185 nm), longer channel lengths reduce drive strength and slew rate, significantly increasing time error sensitivity. This is seen both in PSS analysis and in transient simulations. The circuit becomes more vulnerable to injected charge, resulting in larger timing errors.
In capacitance scaling (0.2 fF to 150 fF), added capacitive load reduces frequency and slew rate, but the time error sensitivity under impulse injection remains nearly constant due to the increased capacitance itself. As such, C_node × SR remains constant, which is confirmed from PSS simulations. However, transient simulations show a gradual increase since the SET current is spread over part (or multiple cycles) of the oscillation period, leading to strong nonlinear and time variant behavior not captured by the simple PSS model.
Designers could also use frequency dividers, which do not affect oscillator timing errors. Key findings are shown across four figures: (i) inverse slew rate trends, and (ii–iv) time error sensitivity under stage, length, and capacitance scaling — from PSS-based and transient SET analyses, normalized to the 5-stage baseline.
In conclusion, stage count adjustment preserves hardness best, capacitance scaling causes minor vulnerability, and gate length scaling notably worsens SEPT tolerance in radiation-prone environments. The final paper will detail the use cases, simulation methods and design strategies.