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Description
This work presents radiation-tolerant implementations for the SALSA front-end readout ASIC through redundancy methods applied to two median-finding algorithms designed for coherent noise suppression. Bit-wise Median Finder (BWMF) and Combinatorial Sum Median Finder (CSMF) were implemented in TSMC 65nm and IHP 130nm technologies and evaluated in terms of area, power, latency, and flip-flop count. Three redundancy techniques were appliedin this work to compare their impact on area and power: simple TMR, full TMR, and temporal TMR (TTMR). The simple and full TMR approach was applied in both algorithms to establish comparisons and TTMR was applied to CSMF as an improvement.
Summary (500 words)
Several high energy physics experiments suffer from coherent noise affecting their readout electronics. To solve that, SALSA front-end read-out ASIC is the successor of the successful SAMPA chip, which is going to be used in the Electron Ion Collider (EIC) experiment of the Brookhaven National Laboratory, United States. This new integrated circuit features a common mode noise subtraction, a non-linear filter that is based on finding median values between the channels of the chip. To guarantee peak efficiency in the filter’s operation, three hardware implementations for the median finder were designed, implemented and successfully verified in TSMC 65nm technology, with one of them being implemented and fabricated using open-source IHP's 130nm node. In order to ensure radiation tolerance in the ASIC’s operation, this work focuses on studying the implementation of redundancy methods in each algorithm and how they compare in terms of area and power.
The first algorithm designed was based on the Bitonic Sorting algorithm (Figure 5) and it was used as a basis for comparison. The other two novel algorithms were named: 1) Bit-wise median finder (BWMF) (Figure 4), it was based on iteratively finding the partial median until the full value is found; 2) Combinatorial Sum median finder (CSMF) (Figure 6), it was almost full combinatorial block that compares each pair of channel to find the median value.
Those algorithms were implemented using the Cadence flow, with their layouts shown in Figures 1, 2 and 3. Their characteristics are presented in Table 1. The Bitonic algorithm did not show any notable characteristics besides its high power consumption and other average results. The BWMF achieved the lowest area and power consumption, but had a high latency and high flip-flop (FF) count — both problematic in radiation prone environments due to prolonged data exposure. Thus, there is the need for register triplication in case of spatial redundancies. On the other hand the CSMF featured the best latency and flip-flop count, but consumed more power and area.
Therefore, it is possible to study the redundancy methods that best fits each one of those algorithms and at which scenario the algorithm and its redundancy method excels. Three redundancy methods were chosen: simple TMR, full TMR and temporal triple modular redundancy (TTMR). The first one consists in triplicating only the output registers and sending their signal to a voter. The second one consists in triplicating all the logic and sending their signal to a voter. And the last one involves generating a clock with triplicated frequency and sampling the output with that clock, each sample is sent to a voter.
A preview of the redundancy implementation’s results can be seen at Table 2 and 3. This data shows the high cost of full TMR in power and area while also presenting an alternative of utilizing combinatorial algorithms with TTMR as an alternative. For the full article version, a detailed analysis and comparison of algorithms and its redundancy methods will be explored.
