Speaker
Description
Abstract: We present the first measurements for the third revision of the High Pitch digitizer System-on-Chip (HPSoC) , a 9 channel Readout Integrated Circuit (ROIC) prototype. The HPSoC concept is that of a high channel density and scalable waveform digitization ROIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip was fabricated in 65nm technology and targets picosecond-level timing resolution via high speed waveform sampling (in excess of 10 Gsps), autonomous chip triggering and feature extraction. Details on measurements on the full chain pre-amplification and digitization without and with LGAD sensors will be presented.
Summary (500 words)
In recent years, the introduction of very fast optical sensors with extremely low pitches (e.g. Low Gain Avalanche detectors -LGADs) has enabled high-density designs for high energy and nuclear physics detectors offering excellent spatial and timing precision; the performance of detector systems composed of large arrays of such components is currently limited mostly by the readout capabilities of the existing readout electronics. To address these issues, we studied and designed the architecture of the HPSoC, a customized multi-channel waveform digitizing readout that is capable of directly interfacing with state-of-the-art sensor arrays, can extract relevant information from each pixel’s interaction and internally distill such information in a compact digital format, with timing precision at the picoseconds level and capable of sub-pixel spatial precisions at a few tens of micrometers or less. The original design has been described in previous contributions. In this work we concentrate on the improvements and extended functionality of the third chip revision.
In order to demonstrate the feasibility of the design and test some of its critical components, a staged approach was followed: 2 previous prototypes were designed and tested to de-risk the individual components (pre-amplifiers, samplers, timing generators, analog-to-digital converters), and full individual channels. A third prototype, HPSoCv3, comprising 9 channels capable of external triggering, individual self-triggering, and feature extraction, with a fast serial interface for data streaming, was designed and fabricated in 65nm CMOS technology.
The new chip packages 9 of the channels whose base functionality had been tested in the previous revisions, wIth additional I/O features (LVDS I/O for reference clocks, conversion clocks and fast serial interface) and an autonomous digital control capable of coordinated multi-channel readout. Furthermore, a digital feature extraction has been integrated that is in principle capable of providing high quality timing and energy (charge) information with programmable features to adapt to different types of input signals.
The fabricated dies will be direct-bonded to a test board that was designed to permit testing via calibration inputs, as well as connection to various types of sensors. Furthermore, the board will allow interfacing with a flexible readout controlled via an external FPGA to fully exercise the new features of the chip.
We will report on the performance of the channels as well as the proven functionality of the new components of the chip, via calibration input signals, and signals generated using AC-LGAD strip and pixel sensors. Sensors with varying strip lengths and thus different input capacitance for the HPSoC will be shown.
The new chip has been designed in modular fashion and upon successful verification, a full-scale HPSoC can be built that will be capable of up to 100 channel readout, with the elementary module built as a copy of the HPSoCv3.
