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Description
This report presents a single-channel readout chip LATRIC0 designed for the CEPC Out Tracker detector. The chip integrates an event-driven ring oscillator time-to-digital converter in a 55 nm process, achieving an average bin-size of 28.9 ps for both time over threshold and time of arrival. The average power consumption for measurement is below 1 mW. To mitigate the inconsistencies between each bin sizes, quantization cells are carefully customized. Both the simulated integral and differential non-linearity are below 0.25 LSB. The power consumption of the pre-amplifier and TDC block is less than 7 mW.
Summary (500 words)
AC-coupled Low Gain Avalanche Detector (AC-LGAD) based microstrip, achieving 30 ps timing resolution with a 100 µm pitch, is proposed to the OTK in CEPC. The AC-LGAD's inherent capacitance poses substantial challenges for power optimization. To match the strip pitch, a LGAD Timing Readout Integrated Chip ( LATRIC) integrating 128 channels with a height of <100 µm per channel is proposed. A single-channel prototype, LATRIC0, serves for functional verification, integrating an front-end amplifier, a time-to-digital converter (TDC) core, and two serializers for encoded and raw data outputs, as illustrated in Figure 1.
The TDC core comprises three parts: a timing controller, an event-driven ring oscillator with quantization logic，and an encoder. When an event occurs, the timing controller generates an enable signal to activate the ring oscillator, along with two latch signals for time of arrival (TOA) and time over threshold (TOT) measurements. A calibration (CAL) is implemented through an additional clock cycle in the latch signal (CAL_latch) . The shared ring oscillator consisting of 15 delay cells supports simultaneous TOA, TOT, and CAL measurements. The delay cell is based on an optimized Nand gate with an average delay of 28.9 ps. Each event produces 111-bit raw data and 36-bit encoded data, covering fine dynamic ranges of 0~50 ns for TOA and 75 ps~50 ns for TOT. Figure 2 shows the quantization timing.
To address inconsistency, a single-to-differential converter transforms each rising or falling edges of the ring oscillator into aligned complementary signals for the SR latch. A symmetric design ensures uniform response to both edge polarities for latch, minimizing inconsistency. Post-simulation results demonstrate a stable bin-size distribution, as depicted in Figure 3. The DNL and INL are both below 0.25 LSB. The TDC core achieves a compact layout height of less than 65 µm with 1 mW active power consumption during quantization. The event-driven scheme significantly reduces the standby power to less than 20 µW, while maintaining average power consumption below 100 µW at <100 kHz hit rate. The simulated results show that the design meet the requirements of the CEPC OTK detector.
LATRIC0 integrates a silicon-proven preamplifier with a measured root mean square jitter of 8 ps, and a power consumption of 6 mW. Therefore, the entire time precision and power consumption are estimated at 16.3 ps and 6.1 mW, respectively, at 100 kHz hit rate. For analysis and debugging, a 128-bit slow-speed serializer and a 40-bit high-speed serializer transmit raw and encoded data, respectively. LATRIC0 has been submitted for fabrication, with detailed design and test results to be presented in the subsequent report.
