Speaker
Description
In this work we report on the development of a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and can supply up to 1A at a voltage of 1.1 to 1.4V. Simulated PSRR at DC is -56dB. Safety features such as load overcurrent protection and the ability to shunt the current of failed parallel SLDOs are included. A first prototype has been submitted. In this work we will report simulation results and early test results.
Summary (500 words)
The Electron Ion Collider (EIC) plans to make use of an edited version of the MOSAIX chip to construct its outer barrel layers [1] with the goal of reducing design risk and effort. However, integrating a chip intended for use as a single unit in the inner barrel into multi-chip staves requires adaptation. Power distribution and slow control connections to multiple chips must now be provided. This mostly involves converting parallel to serial interfaces to reduce cabling and detector mass. Since this implies serial powering, the small negative back bias required by MOSAIX must also now be generated individually for each chip, relative to the local ground.
The original intention was to integrate these functions into the edited MOSAIX. However, practical considerations require placing them in a separate chip referred to as the Ancillary ASIC (AncASIC), which will support the MOSAIX derived device (Figure 1). This will be fabricated in the XFAB XT011 SOI process. This process choice is mainly driven by the requirement to generate a negative voltage (SOI permits isolated transistors), but it is also suited to power applications. In this work we describe the Shunt LDO (SLDO) required for the serial powering network.
The SLDO concept is well known [2] and has been adapted for the needs of the EIC. MOSAIX requires 4 supply voltages – GlobalDigital, GlobalAnalog, Services and Serialiser. Four SLDOs will therefore be needed to supply MOSAIX. These supplies have currents ranging from 30mA to 900mA – a considerable variation. However, to reduce design time and risk, a single SLDO design will be used. This comes at the cost of silicon area, since some power transistors will be much larger than strictly necessary.
Critical SLDO performance parameters are efficiency and Power Supply Rejection Ratio (PSRR). These are complementary quantities which can be tuned by setting the drop-out voltage and the static shunt current. A drop out voltage of around ~200mV, and an additional shunt current of 10% (based on previous studies [2]) have been used. Several protection features are also included.
The design has been completed, and a testbench has been constructed (Figure 2) for evaluation. Functional performance was evaluated first (Figure 3), followed by full corner simulations for efficiency (Figure 4), which varies from 72-79%. PSRR has a simulated minimum of -56dB at DC and a maximum of -13dB at 158kHz (Figure 5). Extracted simulations (Figure 6) and IR Drop analysis (Figure 7) have been performed and show no performance issues and acceptable drops in the power grid.
Simulations indicate the design is functioning as required. The first test structure was submitted in March and is expected in September. Future work will involve characterising this device and integrating it with the other circuits on the AncASIC.
References
[1] Development of a Silicon Vertex and Tracking Detector for the Electron-Ion Collider, L. Gonella, VERTEX 2023, https://doi.org/10.22323/1.448.0038
[2] Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing, Orfanelli, S et al, TWEPP 2017, https://doi.org/10.22323/1.313.0055
