Speaker
Description
This work presents the design, implementation, and characterization of a 28 nm CMOS readout channel for pixel sensors in future HEP experiments. The channel adopts the Time-Over-Threshold technique for the digital conversion of the detector signal amplitude and integrates a low-noise, charge-sensitive amplifier based on a composite cascode gain stage. A prototype chip, featuring an 8x32 array of readout channels, was submitted in Q3-2024 and is currently available for characterization. The paper will discuss the design and the experimental validation of the front-end, focusing on the main analog performance parameters of the channels integrated in the prototype chip.
Summary (500 words)
The 28 nm CMOS technology is rapidly emerging as a robust platform for the development of electronics for high-energy physics experiments in next-generation particle colliders. Compared to the 65 nm process (which is the technology of choice for the pixel readout chips developed by the RD53 collaboration for the phase-II upgrades of the ATLAS and CMS experiments) the 28 nm node offers significant advantages in terms of miniaturization and radiation hardness. Devices designed in this technology have indeed demonstrated excellent performance even after irradiation at total ionizing doses exceeding 1 Grad(SiO2). While enabling the design of smaller pixel cells and the integration of a larger number of digital functionalities at the pixel level, moving to this technology node presents challenges, particularly in analog circuit design. One of the primary challenges is related to the supply voltage, which is limited to a relatively low 0.9 V in this technology and which severely limits the range of viable circuit architectures that can be implemented for the design of analog circuits such as charge-sensitive amplifiers and threshold discriminators. Moreover, advanced processing techniques (such as phase-shifting masks) are used in 28 nm CMOS to improve the precision of the photolithography and reduce feature sizes. While these techniques are crucial for achieving fine resolutions, they also set a number of layout constraints that have to be carefully considered during the design phase.
This work focuses on the development of an asynchronous front-end circuit in 28 nm CMOS leveraging the Time-over-Threshold (ToT) technique to digitize the signal generated by the pixel sensor. It features a compact charge-sensitive amplifier (CSA) with two independent feedback loops, one for signal processing and the other to compensate for the detector leakage current. The signal path includes an n-channel transistor providing (for large input signals) a linear discharge of the CSA feedback capacitance. A differential comparator is connected at the output of the CSA and drives two digital counters (a ToT counter for digitization and a Time-of-Arrival counter to be used, during characterization, for time-walk analysis). A 5-bit, in-pixel DAC is integrated for local threshold tuning.
A prototype chip, including an 8x32 matrix of readout channels with a pitch of 25 um x 100 um, was submitted in September 2024 and is currently available for characterization. The conference paper will provide the reader with a detailed discussion of the design and experimental validation of the front-end channel, with a particular emphasis on the key analog performance parameters such as noise, threshold dispersion and ToT linearity.
