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Description
This work presents a 12-bit ADC implemented in 65 nm CMOS technology, designed for on-chip conversion in high-energy physics experiments, It is also intended for use as an IP block within the DRD7 collaboration framework. The architecture features a fully differential Capacitive DAC, a double-tail latched comparator and an asynchronous digital controller. Post-layout simulations demonstrate an ENOB of 11.6 bits at 50 MSps with a power consumption kept below 850 µW at this rate. This work aims at exploring the performance boundaries of SAR architectures in 65 nm technology. Full characterization of the ADC will be conducted later this year.
Summary (500 words)
High-energy physics experiments require detectors with ever-increasing speed, high channel density, and precise signal amplitude measurement in each channel. Given the high channel count, amplitude digitization must be performed with ultra-low power consumption per channel. Otherwise, the total power demand would exceed the maximum allowable power density of the ASIC. This work is intended to be integrated into the work-package 7.3a of the DRD7 collaboration.
The Successive Approximation Register (SAR) architecture has demonstrated high efficiency for moderate-resolution, moderate-speed analog-to-digital conversion [1]. The proposed ADC design operates in a fully differential configuration and employs the Merged Capacitor Switching (MCS) scheme [2], one of the most energy-efficient switching techniques reported.
To support a near rail-to-rail input range, the comparator is implemented as a latched, double-tail architecture with a complementary input differential pair (NMOS and PMOS). The approximation logic is asynchronous, whereas the start-of-conversion (SoC) signal and output registers are synchronized with the digital core.
The 11-bit Capacitive DAC is segmented using a bridge capacitor, allowing the main DAC to view the sub-DAC as additional binary-weighted capacitors with negative exponents. A critical design challenge is tuning the bridge capacitor to balance both DAC segments. Furthermore, parasitic capacitance introduced during layout may exacerbate mismatches. Although the bridge capacitor is slightly larger than the unit capacitor by design, this implementation uses a unit LSB capacitor and a calibration mechanism. Two independent reference voltages are employed to compensate for both deterministic and random mismatches.
To achieve full input range, a bootstrap switch is utilized. Following the architecture proposed by Ramkaj et al. [3], reducing the gate capacitance of the switch is key to proper bootstrapping. The CMOS process used in this work supports triple-well connections, enabling the bulk of the main switch to be connected to the bottom plate of the bootstrap capacitor. This configuration lowers the on-resistance during tracking and increases off- resistance when open, enhancing switch performance.
Post-layout simulations demonstrate a Signal-to-Noise Distortion Ratio (SNDR) of 71.41 dB, equivalent to an Effective Number Of Bits (ENOB) of 11.57 bits, at a sampling rate of
50 MSps and power consumption below 850 µW at this rate. For lower occupancies the power consumption will decrease accordingly. This corresponds to a Walden figure of merit (FoM) of 5.51 fJ/conv.
The first prototype has been submitted for fabrication and should be produced before the conference. Preliminary measurement results will be shared as available. A second iteration, expected by the end of Q3 2025, will include a Reference Voltage Buffer (RVB) to enable DAC calibration.
Figures attached: Survey of SNDR and Walden FoM versus sampling frequency compared to this work, with data compiled from [4] for SAR ADCs
References:
[1] J. Fredenburg et al., doi: 10.1109/CICC.2015.7338380.
[2] Sang-Min Yoo et al., doi: 10.1109/TCSII.2004.827555.
[3] A. Ramkaj et al., doi: 10.1109/PRIME.2015.7251337.
[4] B. Murmann, ADC Performance Survey 1997-2024. [Online]. Available: https : / /
github.com/bmurmann/ADC-survey.