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Description
The ALICE ITS3 project develops a wafer-scale monolithic stitched pixel detector chip of 27~cm lengths. One of the main challenges in such a design is to transmit data from the 144 pixel matrices (or tiles) to the Left End-Cap (LEC) region where the readout processor is located, without compromising power consumption, noise coupled into front-ends, and the active pixel area. This contribution presents data transmission schemes implemented in the first stitched wafer prototypes (MOSS and MOST), and a new design approach based on differential, low-voltage swing for wafer-scale on-chip data transmission that significantly improves the performance of the previous implementations.
Summary (500 words)
The Inner Tracking System 3 (ITS3) is a wafer-scale monolithic pixel detector replacing the 3 innermost ALICE tracking system layers. Instead of the typical chip size, limited to the reticle dimensions of the lithography process, the design of a wafer-scale sensor chip is made possible using the stitching technique. To assess stitching feasibility in yield and performance, two \textbf{M}onolithic \textbf{S}titched \textbf{S}ensors, MOSS and MOST (for timing), have already been manufactured and measured.
MOSAIX is the second generation of the stitched sensor development and is the full-size prototype of the ITS3 sensor chip. This design combines the features and knowledge obtained from the previous design prototypes. Each MOSAIX chip consists of 144 identical pixel matrix tiles that combine, in the periphery, data from the neighboring pixel region to be sent to the Left End-Cap, where the data is aggregated and sent off-chip through 10~Gbps serializers. The data transmission in the previous prototype, also known as the stitched backbone (SBB), was implemented using CMOS buffers carrying data through several centimeters along the chip. Despite the simplicity, this approach had several disadvantages. In the case of MOSS, the SBB was implemented in the peripheral region of the pixels with single-ended CMOS buffers repeated every 3.2~mm, sending data only up to 40~Mbps. These inverter-based buffers were charging and discharging the parasitic capacitance of the line (of a few pF) to $V_{DD}$ and $V_{SS}$, causing considerable power dissipation and current spikes.
The data links implemented in MOSAIX rely on a differential transmission architecture with a low-voltage swing. The main advantages are power efficiency, immunity to supply noise, and reduction of noise injection into sensing nodes, allowing for the physical implementation of the data lines on top of the pixel region without affecting analog performance. These buffers send data up to 160~Mbps for a distance of $\sim$12~mm with a consumption of $\sim$1~pJ/bit/cm, achieving an improvement compared to MOSS, in terms of speed and distance of $\sim$$4\times$ and more than $3\times$ regarding power consumption. The data buffer comprises a receiver (RX) and transmitter (TX). The RX uses a dynamic comparator to sample the input sequence and an SR flip-flop to hold the state. The TX is built with a programmable capacitive driver, as the series capacitance reduces the voltage swing along the line to $\sim100\mathrm{mV_{pp-diff}}$, reducing dynamic power consumption, since the power is $\propto C_{line}\cdot {V_{DD}}^2$. Due to the capacitive nature of the driver, a 1-bit current-steering DAC is added at the TX side and a resistor at the RX side to define the DC level, avoiding the need for a DC-balanced data stream. To ensure reliable data capture and to mitigate the risk of metastability along the 2$\times$26 cm clock and data path, extensive post-layout simulations have been conducted to validate both performance and the static/dynamic timing paths.
This work addresses the performance and learnings from wafer-scale transmission on the prototypes, key challenges encountered in designing wafer-scale on-chip data transmission for the MOSAIX sensor chip, and the impact of single-event transient (SET) effects.
