Speaker
Description
The SALSA chip will be a versatile ASIC designed for various MPGD applications, including TPCs, trackers, and photon counting. It will feature 64 channels with tunable front-ends and fast ADCs, and a configurable DSP for data correction and feature extraction. The frontend includes a high open loop gain CSA, a pole-zero cancellation circuit, and a shaper, with four dynamic ranges and eight peaking times. Four ASIC prototypes have already been designed and tested to validate the main analog building blocks of the future SALSA chip: analog channel, ADC, PLL, analog and digital probes, I2C, etc.
Summary (500 words)
The SALSA chip is a future versatile ASIC adaptable to various types of MPGD applications, such as TPCs, trackers, photon counting.
The baseline of the SALSA specifications comes from the future ePIC experiment at EIC: it is foreseen to read the curved resistive Micromegas tiles of its central tracker. Nevertheless, the specifications are voluntarily extended to cover the needs of the uRWell ladders and discs of the experiment, as well as other challenging applications in future.
The final SALSA chip will integrate 64 channels, each including a tunable front-end and a fast ADC. A highly configurable DSP performs per-channel and inter-channel data correction to extract the shape, amplitude and timing features from incoming signals and to match the output data flux to the bandwidth of four 1Gb/s serial links. SALSA will be compatible with the continuous streaming readout foreseen for the experiment, but will also work in a triggered environment. SALSA is being designed to detect MPGD signals, which, in ePIC, are in the order of 50-250 ns long, with typical charges ranging from few 10 fC up to 250 fC, and that require noise levels of less than 0.5 fC. A typical input capacitance can range from few tens of pF with close detectors and up to 1 nF with remote off-detector frontends. In ePIC, the tracker readout will be exposed to a mild radiation environment, with doses in the order of 10 krad and 10¹¹ n/cm² over a period of 10 years, and to a magnetic field of 2 T. The expected signal rate will be in the order of 10 kHz per channel. The targeted time precision is of the order of 10 ns.
The frontend is based on a high open loop gain (80dB) charge sensitive amplifier (CSA), a pole-zero cancellation circuit and a shaper, able to read signals of both polarities. The CSA features a tunable size input transistor to make it adaptable to the input capacitance of the channel. Four dynamic ranges are implemented: 50 fC, 250 fC, 500 fC or 5 pC. Eight different peaking times are available from 50 ns to 500 ns. An anti-saturation circuit is integrated to limit crosstalk and deadtime. The ADC is based on a successive approximation register (SAR) architecture with a 12-bit resolution and a maximum sampling rate of 50 MS/s.
The SALSA ASIC will integrate a DSP applying pedestal equalization, a common mode noise subtraction, a baseline following correction, an infinite impulse filtering, and finally a low-amplitude sample suppression. External triggers will be managed by the DSP to select specifically samples present within a programmable time window. Trigger primitives will be generated when samples above threshold will be observed, with conditions on channel multiplicities.
Four ASIC prototypes have already been designed and tested to validate the main building blocks of the future SALSA chip: analog channel, ADC, PLL, analog and digital probes, I2C, etc. The main results obtained with these building blocks will be presented and the next steps of the project will be outlined.