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Description
SALSA1 is a test chip preparing the SALSA design, a reconfigurable readout ASIC for MPGD detectors designed in TSMC 65 nm. SALSA1 includes different analogue, mixed and digital blocks to be tested to evaluate the best options for SALSA. The chip is highly reconfigurable to adapt to a large diversity of situations, managing different gains, polarities and different peaking times, expected to reach up to 100kHz counting rates. Two different analogue channels and two different ADC, producing four configurations, are tested. The tests on the chip, received in January 2025, gave valuable insights to compare those configurations.
Summary (500 words)
The SALSA chip is a future reconfigurable readout ASIC, to be integrated in the future EPIC tracker of the EIC experiment (BNL, USA) and read different types of MPGD detectors.
SALSA1 is a first ASIC made to prepare SALSA design. It aims at testing and evaluating several analogues, mixed and digital blocs meeting with SALSA specifications but also anticipating future needs of experiments with higher activity rate.
It uses a low-node technology, TSMC 65 nm, and is highly reconfigurable with up to 40 parameters for the analogue part only, for gain control, PZC configuration and pulse shaping filters adjustments among others controllable features. Therefore, SALSA1 allows acquisition of signals of different amplitude or polarity. The signals are acquired at 50 MHz by the ADCs. The digital part multiplexes the data, allows continuous readout and manage the slow control.
SALSA1 implements four different combinations of two different analogue front-ends and two ADC architectures. The analogue channels consist of a Charge Sensitive Amplifier (CSA) a pole zero compensation (PZC), a shaper, a gain stage and a single to differential buffers.
Channel 0 and 2 implement a Krummenacher PZC and Channel 1 and 3 an attenuating current conveyor PZC. Channel 0 and 1 implement a SAR ADC using a resistor ladder for coarse bits pre-determination and Channel 2 and 4 a SAR-TDC ADC.
Thanks to the tests of these channels, we will be able to compare the architectures, weight the different trade-offs and chose the best one for the next chip version. SALSA1 was back from foundry in January 2025. Its testbench uses python script controlling a commercial board connected to a generic ASIC characterization board, itself connected to the dedicated SALSA1 board. A voltage pulse on the internal capacitor creates the charge injection used as input.
The first test series gave few insights on the block’s performances. Krummenacher PZC have less overshoot than the attenuating current conveyor one but suffers from significant longer tails. Krummenacher PZC will more likely limits the activity range to 10k or 20k events/s while we’re hoping to reach 100k events/s. For channel 0 with a gain of 15 mV/fC, and a peaking time of 500 us, we have an equivalent noise charge (ENC) of 600. In the same configuration channel 1 has a gain of 12 mV/fC and a similar ENC. This illustrates the trade-offs between speed and noise.
Further tests results will be presented to explore more widely SALSA1 performances.
