Speaker
Description
The upgrade of the ALICE vertex detector (ITS3) with wafer-scale stitched MAPS targets an orthogonal MIP detection efficiency >99%, with a fake-hit rate <0.1pixel⁻¹s⁻¹ and a power budget of 40mW/cm². The MOSS wafer-scale monolithic sensor analog front-end, featuring ~0.55mV/e- gain and ~16e- rms of noise and threshold dispersion, was designed, prototyped and measured confirming these performance targets. Measurement results suggest that the digital readout signal (STROBE) injects noise into the pixel matrix, indicating an even better effective front-end. In this work, front-end design, simulation and measurement results will be presented together with a discussion on the observed STROBE-related effect.
Summary (500 words)
The Monolithic Stitched Sensor (MOSS) is a prototype monolithic sensor ASIC developed for the upgrade of the ALICE Inner Tracking System (ITS3) at CERN. Designed in a 65nm CMOS imaging technology, it uses stitching to cover a large area (25.9cm × 1.4cm) within a single die. To allow the minimisation of the detector material budget (0.09%X0/layer), power and data transmission are integrated on chip. One of the consequences is the extremely low power allocated for the analog front-end, in the order of 30nW/pixel. MOSS integrates two distinct pixel matrices: one with 256x256 pixels and a pitch of 22.5µm; the second one with 320x320 pixels and a pitch of 18µm. The analog pixel, which includes the front-end, decoupling capacitance and analog pulsing circuitry, occupies an area of ~80µm2. The sensor features a small (~1µm²) collection electrode and a capacitance of <5fF.
The analog front-end is a continuously active circuit responsible for resetting the collection electrode, amplifying the generated charge (sensor MIP is ~600e-), and digitizing the signal via a discrimination stage. It is optimized to take full advantage of the small sensor capacitance. Unlike standard charge-sensitive amplifiers (CSA), where charge is integrated on the feedback capacitor, this front-end integrates charge directly on the sensor capacitance. This prevents excessive loading of the input node improving the overall performance.
A key design feature is the inclusion of a level shifter in the first amplification stage. This shifts the input node voltage closer to the supply rail, allowing for a higher sensor reverse bias. As a result, the bulk can be biased at a low voltage (or even 0V), eliminating the need for a large bulk supply that could negatively impact NMOS transistor reliability. At the same time, this ensures sufficient sensor depletion, maintaining a low sensor capacitance for optimal charge collection.
Simulations predict a front-end gain of ~0.55mV/e⁻ with a back bias of 0V. The circuit demonstrates low noise (~16e⁻ rms) and minimal threshold dispersion due to mismatch (~16e⁻ rms), both of which are confirmed by measurements. This enables the front-end to meet the ITS3 performance targets, achieving an orthogonal MIP detection efficiency above 99% while keeping the fake-hit rate below 0.1 pixel⁻¹s⁻¹. However, measurements reveal a systematic horizontal trend in the fake-hit rate across the matrix. Investigations suggest that the global digital readout signal (STROBE) injects noise into the analog domain. This indicates that the true performance of the front-end is better than initially measured, and resolving this issue will further expand its operating window.
These findings provided valuable input for the full-functionality sensor prototype, MOSAIX. Design improvements include refined bias distribution, further optimization of the analog front-end, and enhanced isolation between digital and analog domain to ensure robust performance across the entire matrix.
In this work, front-end design will be presented, simulation and measurement results will be discussed while highlighting key observations related to performance optimization and future improvements.
