Speaker
Description
The PRISME chip is developed as a new radiation tolerant PLL for clock generation with a jitter lower than ten ps. This block is designed in the TSMC 65 nm technology, to allow its integration in future readout ASICs that are considered for the EIC project. The PLL block is a basis of a low-power standalone clock fan-out ASIC with phase adjustment capabilities. A first prototype was design and tests showed that the nominal PLL frequency was reached with a wide input frequency range. The PRISMEv1 will come back from foundry in May 2025 implementing the improved noise performance PLL.
Summary (500 words)
Nowadays frontend electronics of modern particle physics experiments require very precise clock signals for different elements in the readout chain. Clock distribution systems, analog and time to digital converters, gigabit serial links, are examples of the components that require clock signals with very low jitter.
The proposed PRISME chip is developed as a new radiation tolerant Phase-Locked Loop (PLL) IP block for clock signal generation with a jitter lower than ten ps. This block is designed in the modern TSMC 65 nm technology, to allow its integration in future readout ASICs that are considered for the EIC project, and in particular, in the "SALSA" MPGD readout chip our groups are presently developing. The PLL block is a basis of a low-power standalone clock fan-out ASIC with phase adjustment capabilities, which might be needed for specific EIC frontend applications.
In this design, we had the opportunity to introduce an optional digital path in the loop control. In particular, an integral digital regulation holds a promise to bring a better stability and improve jitter characteristics of the PLL. The digital regulation is included in the design and presents a noticeable improvement of jitter figures while requiring low additional area and power.
A first PRISMEv0 prototype was received in 2023 and tests showed that the nominal 3.2 GHz PLL frequency was reached with a wide input frequency range, and clock signals were generated with a very low random jitter of 2.5 ps RMS. An updated prototype design named PRISMEv1 correcting some unexpected deterministic jitter was submitted in December 2024.
The new PRISMEv1 ASIC will come back from foundry in May 2025 implementing the improved noise performance PLL, the four programmable clock outputs, internal temperature and radiation sensors, a triplicated I2C slow control and a CDR. The latest tests from the former PRISMEv0 prototype in TID and in laboratory has shown very encouraging results and we expect to present the improved performances from the PRISMEv1 design at the conference.
